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1.发明授权Method system and apparatus for instruction execution tracing with out of order processors 失效无序处理器的指令执行跟踪方法系统和装置公开(公告)号：US06681321B1
公开(公告)日：2004-01-20
申请号：US09552856
申请日：2000-04-20
申请人： Jason N. Dale , Jim A. Kahle , Douglas R. Logan , Alex E. Mericas , William J. Starke , Philip L. Vitale
发明人： Jason N. Dale , Jim A. Kahle , Douglas R. Logan , Alex E. Mericas , William J. Starke , Philip L. Vitale
IPC分类号： G06F1100
CPC分类号： G06F11/3636
摘要： A method, system and apparatus for instruction execution tracing with out of order speculative processors. Information corresponding to the state of an instruction cache and a data cache is stored in a trace storage device along with information corresponding to instructions sequenced and executed by the processor. When a cache load is necessary, updated cache information is stored in the trace storage device. Thereby, the state of the cache at all times during execution of instructions may be known from the information stored in the trace storage device. Additionally, the particular instructions sequenced and executed is known from the sequenced instructions information and the executed instructions information stored in the trace storage device. Hence the instruction execution stream may be reconstructed from the information stored in the trace storage device.
摘要翻译： 用于无序推测处理器的指令执行跟踪的方法，系统和装置。 与指令高速缓存和数据高速缓存的状态相对应的信息与跟随由处理器排序并执行的指令对应的信息一起存储在跟踪存储设备中。 当需要缓存加载时，更新的缓存信息被存储在跟踪存储设备中。 因此，可以从存储在跟踪存储装置中的信息中知道执行指令期间的所有时间的高速缓存的状态。 此外，根据存储在跟踪存储设备中的排序指令信息和执行的指令信息，已知排序并执行的特定指令。 因此，可以从存储在跟踪存储设备中的信息重建指令执行流。
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2.发明授权Managing an out-of-order asynchronous heterogeneous remote direct memory access (RDMA) message queue 有权管理异步异步异构远程直接内存访问（RDMA）消息队列公开(公告)号：US08904064B2
公开(公告)日：2014-12-02
申请号：US12257577
申请日：2008-10-24
CPC分类号： G06F13/28
摘要： A system and method operable to manage a message queue is provided. This management may involve out-of-order asynchronous heterogeneous remote direct memory access (RDMA) to the message queue. This system includes a pair of processing devices, a primary processing device and an additional processing device, a memory in storage location and a data bus coupled to the processing devices. The processing devices cooperate to process queue data within a shared message queue wherein when an individual processing device successfully accesses queue data the queue data is locked for the exclusive use of the processing device. When the processing device acquires the queue data, the queue data is locked and the queue data acquired by the acquiring processing device includes the queue data for both the primary processing device and additional processing device such that the processing device has all queue data necessary to process the data and return processed queue data.
摘要翻译： 提供了一种可操作以管理消息队列的系统和方法。 该管理可能涉及到消息队列的无序异步异构远程直接存储器访问（RDMA）。 该系统包括一对处理设备，主处理设备和附加处理设备，存储位置中的存储器和耦合到处理设备的数据总线。 处理设备协作来处理共享消息队列中的队列数据，其中当单个处理设备成功地访问队列数据时，队列数据被锁定以供处理设备的专用使用。 当处理装置获取队列数据时，队列数据被锁定，并且由获取处理装置获取的队列数据包括用于主处理装置和附加处理装置的队列数据，使得处理装置具有处理所需的所有队列数据 数据和返回处理的队列数据。
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3.发明授权Assigning efficiently referenced globally unique identifiers in a multi-core environment 有权在多核环境中分配高效引用的全局唯一标识符公开(公告)号：US08316207B2
公开(公告)日：2012-11-20
申请号：US12649542
申请日：2009-12-30
IPC分类号： G06F12/02
CPC分类号： G06F12/0284 , G06F12/0692 , G06F2212/1016
摘要： A mechanism is provided in a multi-core environment for assigning a globally unique core identifier. A Power PC® processor unit (PPU) determines an index alias corresponding to a natural index to a location in local storage (LS) memory. A synergistic processor unit (SPU) corresponding to the PPU translates the natural index to a first address in a core's memory, as well as translates the index alias to a second address in the core's memory. Responsive to the second address exceeding a physical memory size, the load store unit of the SPU truncates the second address to a usable range of address space in systems that do not map an address space. The second address and the first address point to the same physical location in the core's memory. In addition, the aliasing using index aliases also preserves the ability to combine persistent indices with relative indices without creating holes in a relative index map.
摘要翻译： 在多核环境中提供了用于分配全局唯一的核心标识符的机制。 PowerPC®处理器单元（PPU）确定对应于本地存储（LS）存储器中的位置的自然索引的索引别名。 对应于PPU的协同处理器单元（SPU）将自然索引转换为核心存储器中的第一个地址，并将索引别名转换为核心内存中的第二个地址。 响应于超出物理内存大小的第二地址，SPU的加载存储单元在不映射地址空间的系统中将第二地址截断到可用的地址空间范围。 第二个地址和第一个地址指向核心内存中相同的物理位置。 此外，使用索引别名的混叠还保留了将持续索引与相对索引相结合的能力，而不会在相对索引图中创建空洞。
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公开(公告)号：US08037293B2
公开(公告)日：2011-10-11
申请号：US12130128
申请日：2008-05-30
IPC分类号： G06F9/00 , G06F15/177
CPC分类号： G06F21/575 , G06F9/4416
摘要： Pervasive logic is provided that includes a random event generator. The random event generator randomly selects which processor of a plurality of processors in the multiprocessor system is to be a boot processor for the multiprocessor system. A corresponding configuration bit for the randomly selected processor is set to identify the processor as a boot processor. Based on the setting of the configuration bits for each processor in the plurality of processors, a selection of a security key is made. The security key is then used to decrypt the boot code for booting the multiprocessor system. Only the randomly selected boot processor is able to select the correct security key for correctly decrypting the boot code, which it then executes to bring the system to an operational state.
摘要翻译： 提供包括随机事件发生器的普遍逻辑。 随机事件发生器随机选择多处理器系统中的多个处理器的哪个处理器是多处理器系统的引导处理器。 设置用于随机选择的处理器的相应配置位以将处理器识别为引导处理器。 基于多个处理器中的每个处理器的配置位的设置，进行安全密钥的选择。 然后，安全密钥用于解密引导代码以引导多处理器系统。 只有随机选择的引导处理器能够选择正确解密引导代码的正确的安全密钥，然后执行该引导代码才能使系统处于运行状态。
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公开(公告)号：US08918552B2
公开(公告)日：2014-12-23
申请号：US12257573
申请日：2008-10-24
CPC分类号： G06F13/28 , G06F5/01 , G06F12/1081
摘要： A system and method operable to manage misaligned direct memory access (DMA) data transfers is provided. This method involves determining a delta between N bytes of data to be copied from within a local side buffer (source location) to a remote buffer (destination location). After the delta is determined a tail of the same length is copied to temporary storage. Then the N bytes of data on the local side buffer minus the tail will be shifted to align the N bytes of data to be copied from within the local side buffer to the starting address of the destination location in the remote buffer. The pre-shifted N bytes of data within the local side buffer may be DMA transferred to the remote buffer. The tail transferred to temporary storage may then be copied from temporary storage to the remote buffer.
摘要翻译： 提供了一种用于管理不对准的直接存储器访问（DMA）数据传输的系统和方法。 该方法涉及从本地侧缓冲器（源位置）到远程缓冲器（目的地位置）之间确定要复制的N字节数据之间的差值。 在确定增量后，将相同长度的尾部复制到临时存储。 然后，本地缓冲区减去尾部的N字节数据将被移位，以将要从本地缓冲区中复制的N个字节的数据对齐到远程缓冲区中目标位置的起始地址。 本地侧缓冲区内的预先移位的N字节的数据可以被DMA传送到远程缓冲器。 转移到临时存储的尾部可以从临时存储器复制到远程缓冲区。
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公开(公告)号：US08856453B2
公开(公告)日：2014-10-07
申请号：US13410260
申请日：2012-03-01
申请人： Jason N. Dale , Miles R. Dooley , Richard J. Eickemeyer , Bradly G. Frey , Yaoqing Gao , Francis P. O'Connell , Jeffrey A. Stuecheli
发明人： Jason N. Dale , Miles R. Dooley , Richard J. Eickemeyer , Bradly G. Frey , Yaoqing Gao , Francis P. O'Connell , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F9/383 , G06F2212/6028
摘要： A prefetch unit includes a transience register and a length register. The transience register hosts an indication of transient for data stream prefetching. The length register hosts an indication of a stream length for data stream prefetching. The prefetch unit monitors the transience register and the length register. The prefetch unit generates prefetch requests of data streams with a transient property up to the stream length limit when the transience register indicates transient and the length register indicates the stream length limit for data stream prefetching. A cache controller coupled with the prefetch unit implements a cache replacement policy and cache coherence protocols. The cache controller writes data supplied from memory responsive to the prefetch requests into cache with an indication of transient. The cache controller victimizes cache lines with an indication of transient independent of the cache replacement policy.
摘要翻译： 预取单元包括一个过渡寄存器和一个长度寄存器。 Transient寄存器容纳数据流预取的瞬态指示。 长度寄存器托管用于数据流预取的流长度的指示。 预取单元监视临时寄存器和长度寄存器。 当Transient寄存器指示瞬态时，预取单元产生具有直到流长度限制的瞬态特性的数据流的预取请求，并且长度寄存器指示数据流预取的流长度限制。 与预取单元耦合的高速缓存控制器实现高速缓存替换策略和高速缓存一致性协议。 高速缓存控制器将响应于预取请求的从存储器提供的数据写入高速缓存中，并显示瞬时信号。 高速缓存控制器使高速缓存行受到与缓存替换策略无关的暂态指示。
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公开(公告)号：US20080229092A1
公开(公告)日：2008-09-18
申请号：US12130185
申请日：2008-05-30
IPC分类号： G06F9/00
CPC分类号： G06F21/575 , G06F9/4405 , G06F15/177 , G06F21/755
摘要： Boot code is partitioned into a plurality of boot code partitions. Processors of a multiprocessor system are selected to be boot processors and are each provided with a boot code partition to execute in a predetermined boot code sequence. Each processor executes its boot code partition in accordance with the boot code sequence and signals to a next processor the successful and uncompromised execution of its boot code partition. If any of the processors does not signal successful completion and/or uncompromised execution of its boot code partition, the boot operation fails. The processors may be arranged, with regard to the boot operation, in a daisy chain, ring, or master/slave arrangement, for example.
摘要翻译： 引导代码被分割成多个引导代码分区。 多处理器系统的处理器被选择为引导处理器，并且每个具有引导代码分区以在预定引导代码序列中执行。 每个处理器根据引导代码序列执行其引导代码分区，并向下一个处理器发送其启动代码分区的成功和不妥协的执行信号。 如果处理器中的任何一个没有显示其启动代码分区的成功完成和/或不妥协的执行，则引导操作失败。 例如，处理器可以针对引导操作被布置在菊花链，环形或主/从装置中。
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8.发明申请Apparatus for Improving Single Thread Performance through Speculative Processing 审中-公开通过投机处理提高单线性能的装置公开(公告)号：US20080201563A1
公开(公告)日：2008-08-21
申请号：US12110400
申请日：2008-04-28
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3824 , G06F9/3851 , G06F9/3863 , G06F9/461
摘要： An apparatus is provided for using multiple thread contexts to improve processing performance of a single thread. When an exceptional instruction is encountered, the exceptional instruction and any predicted instructions are reloaded into a buffer of a first thread context. A state of the register file at the time of encountering the exceptional instruction is maintained in a register file of the first thread context. The instructions in the pipeline are executed speculatively using a second register file in a second thread context. During speculative execution, cache misses may cause loading of data to the cache may be performed. Results of the speculative execution are written to the second register file. When a stopping condition is met, contents of the first register file are copied to the second register file and the reloaded instructions are released to the execution pipeline.
摘要翻译： 提供了一种用于使用多个线程上下文来提高单个线程的处理性能的装置。 当遇到异常指令时，异常指令和任何预测指令被重新加载到第一个线程上下文的缓冲区中。 在遇到异常指令时，寄存器文件的状态被保存在第一个线程上下文的寄存器文件中。 使用第二线程上下文中的第二寄存器文件推测地执行流水线中的指令。 在推测执行期间，高速缓存未命中可能导致数据加载到缓存可能被执行。 推测执行的结果将写入第二个寄存器文件。 当满足停止条件时，将第一寄存器文件的内容复制到第二寄存器文件，并且重新加载的指令被释放到执行管线。
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公开(公告)号：US08046573B2
公开(公告)日：2011-10-25
申请号：US12130105
申请日：2008-05-30
IPC分类号： G06F9/00 , G06F15/177
CPC分类号： G06F15/177 , G06F9/4405 , H04L9/08 , H04L2209/04 , H04L2209/08
摘要： One of the processors of a multiprocessor system is chosen to be a boot processor. The other processors of the multiprocessor system execute masking code that generates electromagnetic and/or thermal signatures that mask the electromagnetic and/or thermal signatures of the actual boot processor. Such masking may involve running the same boot code as the boot processor but without obtaining access to security information, such as the security key for accessing the system. The electromagnetic and/or thermal signatures generated by the execution of the masking code preferably approximate the electromagnetic and/or thermal signatures of the actual boot code executing on the boot processor. In this way, it is difficult to distinguish which processor is the actual boot processor.
摘要翻译： 多处理器系统的处理器之一被选择为引导处理器。 多处理器系统的其他处理器执行掩蔽代码，其产生屏蔽实际引导处理器的电磁和/或热特征的电磁和/或热特征。 这种掩蔽可以涉及运行与引导处理器相同的引导代码，但是不获得诸如用于访问系统的安全密钥之类的安全信息的访问。 通过执行屏蔽码产生的电磁和/或热特征优选近似于在引导处理器上执行的实际引导代码的电磁和/或热特征。 以这种方式，很难区分哪个处理器是实际的引导处理器。
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10.发明申请MANAGING AN OUT-OF-ORDER ASYNCHRONOUS HETEROGENEOUS REMOTE DIRECT MEMORY ACCESS (RDMA) MESSAGE QUEUE 有权管理超出异步异步远程直接存储器访问（RDMA）消息队列公开(公告)号：US20100106948A1
公开(公告)日：2010-04-29
申请号：US12257577
申请日：2008-10-24
CPC分类号： G06F13/28
摘要： A system and method operable to manage a message queue is provided. This management may involve out-of-order asynchronous heterogeneous remote direct memory access (RDMA) to the message queue. This system includes a pair of processing devices, a primary processing device and an additional processing device, a memory in storage location and a data bus coupled to the processing devices. The processing devices cooperate to process queue data within a shared message queue wherein when an individual processing device successfully accesses queue data the queue data is locked for the exclusive use of the processing device. When the processing device acquires the queue data, the queue data is locked and the queue data acquired by the acquiring processing device includes the queue data for both the primary processing device and additional processing device such that the processing device has all queue data necessary to process the data and return processed queue data.
摘要翻译： 提供了一种可操作以管理消息队列的系统和方法。 该管理可能涉及到消息队列的无序异步异构远程直接存储器访问（RDMA）。 该系统包括一对处理设备，主处理设备和附加处理设备，存储位置中的存储器和耦合到处理设备的数据总线。 处理设备协作来处理共享消息队列中的队列数据，其中当单个处理设备成功地访问队列数据时，队列数据被锁定以供处理设备的专用使用。 当处理装置获取队列数据时，队列数据被锁定，并且由获取处理装置获取的队列数据包括用于主处理装置和附加处理装置的队列数据，使得处理装置具有处理所需的所有队列数据 数据和返回处理的队列数据。
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