公开(公告)号：US08689162B2

公开(公告)日：2014-04-01

申请号：US13235908

申请日：2011-09-19

申请人： Jason T. Su ,  Winston Lee

发明人： Jason T. Su ,  Winston Lee

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F2217/84 ,  H03K5/159 ,  H03K2005/00013

摘要： Aspects of the disclosure provide a circuit, such as an integrated circuit. The circuit includes a first circuit and a second circuit. The second circuit includes a delay circuit configured to cause the second circuit to have substantially matched delay characteristics of the first circuit in response to at least one parameter change of manufacturing, environmental and operational parameters, such as process variation, temperature variation, and supply voltage variation.

摘要翻译： 本公开的方面提供了诸如集成电路的电路。 电路包括第一电路和第二电路。 第二电路包括延迟电路，其被配置为响应于制造，环境和操作参数（例如过程变化，温度变化和电源电压）的至少一个参数变化，使得第二电路具有基本匹配的第一电路的延迟特性 变异。

公开(公告)号：US20120068754A1

公开(公告)日：2012-03-22

申请号：US13235908

申请日：2011-09-19

申请人： Jason T. SU ,  Winston Lee

发明人： Jason T. SU ,  Winston Lee

IPC分类号： H03H11/26

CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F2217/84 ,  H03K5/159 ,  H03K2005/00013

摘要： Aspects of the disclosure provide a circuit, such as an integrated circuit. The circuit includes a first circuit and a second circuit. The second circuit includes a delay circuit configured to cause the second circuit to have substantially matched delay characteristics of the first circuit in response to at least one parameter change of manufacturing, environmental and operational parameters, such as process variation, temperature variation, and supply voltage variation.

摘要翻译： 本公开的方面提供了诸如集成电路的电路。 电路包括第一电路和第二电路。 第二电路包括延迟电路，其被配置为响应于制造，环境和操作参数（例如过程变化，温度变化和电源电压）的至少一个参数变化，使得第二电路具有基本匹配的第一电路的延迟特性 变异。

公开(公告)号：US08451041B2

公开(公告)日：2013-05-28

申请号：US13184836

申请日：2011-07-18

申请人： Jason T. Su ,  Winston Lee ,  Yuntian Chen

发明人： Jason T. Su ,  Winston Lee ,  Yuntian Chen

IPC分类号： H03K3/356

CPC分类号： H03K3/356121

摘要： A flip-flop circuit includes a charge injection module, a sense amp module, and a latch module. The charge injection module is configured to, in response to a clock signal, selectively provide electrical charge from a power supply to a first node. The sense amp module is configured to adjust a voltage of a second node in response to detecting a voltage of the first node crossing a threshold while the charge injection module is providing the electrical charge to the first node. The latch module is configured to in response to the clock signal, store a value based on a voltage of the second node. The latch module is also configured to provide the value as an output of the flip-flop circuit.

摘要翻译： 触发器电路包括电荷注入模块，感测放大器模块和锁存模块。 电荷注入模块被配置为响应于时钟信号选择性地从电源向第一节点提供电荷。 感测放大器模块被配置为响应于在电荷注入模块向第一节点提供电荷时检测到跨越阈值的第一节点的电压来调整第二节点的电压。 闩锁模块被配置为响应于时钟信号，存储基于第二节点的电压的值。 锁存模块还被配置为提供该值作为触发器电路的输出。

公开(公告)号：US20120013379A1

公开(公告)日：2012-01-19

申请号：US13184836

申请日：2011-07-18

申请人： Jason T. Su ,  Winston Lee ,  Yuntian Chen

发明人： Jason T. Su ,  Winston Lee ,  Yuntian Chen

IPC分类号： H03K3/356

CPC分类号： H03K3/356121

摘要： A flip-flop circuit includes a charge injection module, a sense amp module, and a latch module. The charge injection module is configured to, in response to a clock signal, selectively provide electrical charge from a power supply to a first node. The sense amp module is configured to adjust a voltage of a second node in response to detecting a voltage of the first node crossing a threshold while the charge injection module is providing the electrical charge to the first node. The latch module is configured to in response to the clock signal, store a value based on a voltage of the second node. The latch module is also configured to provide the value as an output of the flip-flop circuit.

摘要翻译： 触发器电路包括电荷注入模块，感测放大器模块和锁存模块。 电荷注入模块被配置为响应于时钟信号选择性地从电源向第一节点提供电荷。 感测放大器模块被配置为响应于在电荷注入模块向第一节点提供电荷时检测到跨越阈值的第一节点的电压来调整第二节点的电压。 闩锁模块被配置为响应于时钟信号，存储基于第二节点的电压的值。 锁存模块还被配置为提供该值作为触发器电路的输出。

公开(公告)号：US08609528B1

公开(公告)日：2013-12-17

申请号：US13204370

申请日：2011-08-05

申请人： Pantas Sutardja ,  Albert Wu ,  Winston Lee ,  Peter Lee ,  Chien-Chuan Wei ,  Runzi Chang

发明人： Pantas Sutardja ,  Albert Wu ,  Winston Lee ,  Peter Lee ,  Chien-Chuan Wei ,  Runzi Chang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816

摘要： Methods for patterning high-density features are described herein. Embodiments of the present invention provide a method comprising patterning a first subset of a pattern, the first subset configured to form a plurality of lines over the substrate, and patterning a second subset of the pattern, the second subset configured to form a plurality of islands over the substrate, wherein said patterning the first subset and said patterning the second subset comprise at least two separate patterning operations.

摘要翻译： 本文描述了用于图案化高密度特征的方法。 本发明的实施例提供了一种方法，包括对图案的第一子集进行图案化，所述第一子集被配置成在所述衬底上形成多个线，以及图案化所述图案的第二子集，所述第二子集被配置为形成多个岛 其中所述图案化所述第一子集并且所述图案化所述第二子集包括至少两个单独的图案化操作。

公开(公告)号：US08605534B2

公开(公告)日：2013-12-10

申请号：US12878703

申请日：2010-09-09

申请人： Winston Lee ,  Ha Soo Kim

发明人： Winston Lee ,  Ha Soo Kim

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G11C7/02 ,  G11C8/08

摘要： Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory. The method generally includes operating peripheral circuitry at a first voltage from a first power rail, operating a memory array at the first voltage or a second voltage, the memory array being coupled to a second power rail, coupling the first and second power rails during standard operating mode when the memory array operates at the first voltage, otherwise not coupling the first and second power rails, and reducing leakage in the memory array during a leakage reduction mode by reducing a voltage differential between a ground plane in the memory array and the second power rail.

公开(公告)号：US08335878B2

公开(公告)日：2012-12-18

申请号：US12494076

申请日：2009-06-29

申请人： Winston Lee ,  Sehat Sutardja ,  Donald Pannell

发明人： Winston Lee ,  Sehat Sutardja ,  Donald Pannell

IPC分类号： G06F7/00 ,  G11C11/401

CPC分类号： G11C7/1075

摘要： A multiport memory architecture, systems including the same and methods for using the same. The architecture generally includes (a) a memory array; (b) a plurality of ports configured to receive and/or transmit data; and (c) a plurality of port buffers, each of which is configured to transmit the data to and/or receive the data from one or more of the ports, and all of which are configured to (i) transmit the data to the memory array on a first common bus and (ii) receive the data from the memory array on a second common bus. The systems generally include those that embody one or more of the inventive concepts disclosed herein. The methods generally relate to writing blocks of data to, reading blocks of data from, and/or transferring blocks of data across a memory. The present invention advantageously reduces latency in data communications, particularly in network switches, by tightly coupling port buffers to the main memory and advantageously using point-to-point communications over long segments of the memory read and write paths, thereby reducing routing congestion and enabling the elimination of a FIFO. The invention advantageously shrinks chip size and provides increased data transmission rates and throughput, and in preferred embodiments, reduced resistance and/or capacitance in the memory read and write busses.

摘要翻译： 多端口内存架构，系统包括相同以及使用方法。 架构通常包括（a）存储器阵列; （b）配置成接收和/或发送数据的多个端口; 以及（c）多个端口缓冲器，每个端口缓冲器被配置为从一个或多个端口发送数据和/或从一个或多个端口接收数据，并且所有端口缓冲器被配置为（i）将数据发送到存储器 阵列在第一公共总线上，（ii）在第二公共总线上从存储器阵列接收数据。 系统通常包括体现本文公开的一个或多个发明构思的系统。 所述方法通常涉及将数据块写入到数据块，从存储器读取数据块和/或传送数据块。 本发明有利地通过将端口缓冲器紧密地耦合到主存储器并且有利地使用存储器读写路径的长段上的点对点通信来减少数据通信中的特别是网络交换机中的等待时间，从而减少路由拥塞和启用 消除FIFO。 本发明有利地缩小芯片尺寸并提供增加的数据传输速率和吞吐量，并且在优选实施例中，存储器读和写总线中的电阻和/或电容减小。

公开(公告)号：US08203902B2

公开(公告)日：2012-06-19

申请号：US13214543

申请日：2011-08-22

申请人： Pantas Sutardja ,  Winston Lee

发明人： Pantas Sutardja ,  Winston Lee

IPC分类号： G11C8/00

CPC分类号： G11C7/10 ,  G11C7/00 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/12 ,  G11C8/14 ,  G11C2207/2209

摘要： A memory system including a memory array, and a read write/module. The memory includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, in which each memory cell is formed at a corresponding intersection of a bit line and a word line in the memory array. The read/write module is configured to control activation of at least two memory cells in the memory array during a read operation or a write operation, wherein the at least two memory cells activated by the read/write module are located on a different word line and a different bit line in the memory array, and wherein each memory cell coupled to a same bit line of the plurality of bit lines is configured to be written to or read from based on selection of the bit line.

摘要翻译： 包括存储器阵列和读写/模块的存储器系统。 存储器包括多个位线，多个字线和多个存储器单元，其中每个存储器单元形成在存储器阵列中位线和字线的相应交叉点处。 读/写模块被配置为在读操作或写操作期间控制存储器阵列中的至少两个存储单元的激活，其中由读/写模块激活的至少两个存储单元位于不同的字线 以及存储器阵列中的不同的位线，并且其中耦合到所述多个位线中的相同位线的每个存储器单元被配置为基于所述位线的选择被写入或从其读取。

公开(公告)号：US07863709B1

公开(公告)日：2011-01-04

申请号：US12104254

申请日：2008-04-16

申请人： Pantas Sutardja ,  Albert Wu ,  Runzi Chang ,  Chien-Chuan Wei ,  Winston Lee ,  Peter Lee

发明人： Pantas Sutardja ,  Albert Wu ,  Runzi Chang ,  Chien-Chuan Wei ,  Winston Lee ,  Peter Lee

IPC分类号： H01L27/082

CPC分类号： H01L27/1026

摘要： Methods and apparatuses directed to low base resistance bipolar junction transistor (BJT) devices are described herein. A low base resistance BJT device may include a collector layer, a base layer formed on the collector layer, a plurality of isolation trench lines formed in the base layer and extending into the collector layer, and a plurality of polysilicon lines formed on the base layer parallel to and overlapping the plurality of isolation trench lines. The base layer may be N-doped or P-doped.

摘要翻译： 本文描述了针对低基极电阻双极结型晶体管（BJT）器件的方法和装置。 低电阻BJT器件可以包括集电极层，形成在集电极层上的基极层，形成在基极层中并延伸到集电极层中的多个隔离沟槽线，以及形成在基极层上的多个多晶硅线 平行于并重叠多个隔离沟槽线。 基层可以是N掺杂或P掺杂的。

公开(公告)号：US07571287B2

公开(公告)日：2009-08-04

申请号：US10702744

申请日：2003-11-05

申请人： Winston Lee ,  Sehat Sutardja ,  Donald Pannell

发明人： Winston Lee ,  Sehat Sutardja ,  Donald Pannell

IPC分类号： G06F12/00

CPC分类号： G11C7/1075

摘要： A multiport memory architecture, systems including the same and methods for using the same. The architecture generally includes (a) a memory array; (b) a plurality of ports configured to receive and/or transmit data; and (c) a plurality of port buffers, each of which is configured to transmit the data to and/or receive the data from one or more of the ports, and all of which are configured to (i) transmit the data to the memory array on a first common bus and (ii) receive the data from the memory array on a second common bus. The systems generally include those that embody one or more of the inventive concepts disclosed herein. The methods generally relate to writing blocks of data to, reading blocks of data from, and/or transferring blocks of data across a memory. The present invention advantageously reduces latency in data communications, particularly in network switches, by tightly coupling port buffers to the main memory and advantageously using point-to-point communications over long segments of the memory read and write paths, thereby reducing routing congestion and enabling the elimination of a FIFO. The invention advantageously shrinks chip size and provides increased data transmission rates and throughput, and in preferred embodiments, reduced resistance and/or capacitance in the memory read and write busses.

摘要翻译： 多端口内存架构，系统包括相同以及使用方法。 架构通常包括（a）存储器阵列; （b）配置成接收和/或发送数据的多个端口; 以及（c）多个端口缓冲器，每个端口缓冲器被配置为从一个或多个端口发送数据和/或从一个或多个端口接收数据，并且所有端口缓冲器被配置为（i）将数据发送到存储器 阵列在第一公共总线上，（ii）在第二公共总线上从存储器阵列接收数据。 系统通常包括体现本文公开的一个或多个发明构思的系统。 所述方法通常涉及将数据块写入到数据块，从存储器读取数据块和/或传送数据块。 本发明有利地通过将端口缓冲器紧密地耦合到主存储器并且有利地使用存储器读写路径的长段上的点对点通信来减少数据通信中的特别是网络交换机中的等待时间，从而减少路由拥塞和启用 消除FIFO。 本发明有利地缩小芯片尺寸并提供增加的数据传输速率和吞吐量，并且在优选实施例中，存储器读和写总线中的电阻和/或电容减小。