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公开(公告)号：US08161350B2
公开(公告)日：2012-04-17
申请号：US11988252
申请日：2006-06-30
IPC分类号： H03M13/00
CPC分类号： H03M13/1194 , H03M13/1105 , H03M13/116 , H03M13/118 , H03M13/1185 , H03M13/2906
摘要： A communication method and a communication system including a first entity (3) including an information source (9) and a coder device (11) connected by a channel (7) transmitting data to a second entity (5) including a decoder device (13), the coder device (11) coding a data sequence sent by the information source (9) to form a set of code words from a parity check matrix including two matrix areas, each matrix area including a processing matrix, a connecting matrix including only one “1” per column and only one “1” per row, and a triangular matrix, and the decoder device (13) decoding a coded reception signal that is received by the second entity and is derived from the set of code words constructed in accordance with said parity check matrix.
摘要翻译： 一种通信方法和通信系统，包括第一实体（3），包括信息源（9）和编码器装置（11），通过信道（7）连接到包括解码器装置（13）的第二实体（5）的信道 ），编码器装置（11）对由信息源（9）发送的数据序列进行编码，以从包括两个矩阵区域的奇偶校验矩阵形成一组码字，每个矩阵区域包括处理矩阵，仅包括连接矩阵 每列一个“1”，每行仅一个“1”，三角矩阵，解码器装置（13）对由第二实体接收的编码的接收信号进行解码，并从构成的代码字集合 根据所述奇偶校验矩阵。
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公开(公告)号：US08214723B2
公开(公告)日：2012-07-03
申请号：US12223109
申请日：2007-01-18
IPC分类号： H03M13/00
CPC分类号： H03M13/2972 , H03M13/1194 , H03M13/2771 , H03M13/2978 , H03M13/6566
摘要： A method of low latency encoding of an input bit sequence (S0) to yield an encoded bit sequence (S), and a corresponding decoding method, said encoding method including: a first encoding step (E1) applied to bits of the input bit sequence (S0), using a first code; an interleaving step (E3) in which an interleaver interleaves the bits obtained from said first code; and a parity, second encoding step (E4) applied to the bits obtained from said interleaver, using a second code, to generate said encoded bit sequence (S). The parity, second encoding step (E4) starts after a predetermined number Δ of bits have been interleaved, said predetermined number Δ of bits ranging between a first lower number Δi of bits depending on one or more parameters of said interleaving step (E3) and a first higher number Δs of bits corresponding to the total number of bits to be processed during said interleaving step (E3).
摘要翻译： 一种输入比特序列（S0）的低延迟编码以产生编码比特序列（S）的方法和相应的解码方法，所述编码方法包括：第一编码步骤（E1），其应用于输入比特序列 （S0），使用第一代码; 交织步骤（E3），其中交织器交织从所述第一码获得的比特; 以及使用第二代码应用于从所述交织器获得的比特的奇偶校验第二编码步骤（E4），以生成所述编码比特序列（S）。 奇偶校验第二编码步骤（E4）在预定数量＆Dgr之后开始; 的位已被交织，所述预定数量＆Dgr; 根据所述交织步骤（E3）的一个或多个参数和与在所述交织步骤期间要处理的总位数相对应的比特的第一较高数目＆Dgr比特，位于第一较低数字＆amp; （E3）。
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公开(公告)号：US20100287437A1
公开(公告)日：2010-11-11
申请号：US12223109
申请日：2007-01-18
CPC分类号： H03M13/2972 , H03M13/1194 , H03M13/2771 , H03M13/2978 , H03M13/6566
摘要： A method of low latency encoding of an input bit sequence (S0) to yield an encoded bit sequence (S), and a corresponding decoding method, said encoding method including: a first encoding step (E1) applied to bits of the input bit sequence (S0), using a first code; an interleaving step (E3) in which an interleaver interleaves the bits obtained from said first code; and a parity, second encoding step (E4) applied to the bits obtained from said interleaver, using a second code, to generate said encoded bit sequence (S). The parity, second encoding step (E4) starts after a predetermined number Δ of bits have been interleaved, said predetermined number Δ of bits ranging between a first lower number Δi of bits depending on one or more parameters of said interleaving step (E3) and a first higher number Δs of bits corresponding to the total number of bits to be processed during said interleaving step (E3).
摘要翻译： 一种输入比特序列（S0）的低延迟编码以产生编码比特序列（S）的方法和相应的解码方法，所述编码方法包括：第一编码步骤（E1），其应用于输入比特序列 （S0），使用第一代码; 交织步骤（E3），其中交织器交织从所述第一码获得的比特; 以及使用第二代码应用于从所述交织器获得的比特的奇偶校验第二编码步骤（E4），以生成所述编码比特序列（S）。 奇偶校验第二编码步骤（E4）在预定数量＆Dgr之后开始; 的位已被交织，所述预定数量＆Dgr; 根据所述交织步骤（E3）的一个或多个参数和与在所述交织步骤期间要处理的总位数相对应的比特的第一较高数目＆Dgr比特，位于第一较低数字＆amp; （E3）。
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4.发明授权公开(公告)号：US08271851B2
公开(公告)日：2012-09-18
申请号：US12514590
申请日：2007-11-09
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1137
摘要： The invention relates to correcting codes for encoding and decoding a data signal. A signal including data variables is coded into a signal including the data variables and parity variables. The encoding and decoding operations are based on a parity check matrix comprised of a systematic matrix and a parity matrix and having rows corresponding coefficients of parity equations and distributed into decoding windows of same size. In order to increase convergence of the iterative decoding, the elements of at least one column of the systematic matrix associated with a decoding window are “0s”, except for a single element which is a “1”. A data variable is only involved in one equation of the window and not involved in solving the equations of other windows as long as the solving of equations of the window is not achieved.
摘要翻译： 本发明涉及用于对数据信号进行编码和解码的代码。 包括数据变量的信号被编码成包括数据变量和奇偶变量的信号。 编码和解码操作基于由系统矩阵和奇偶校验矩阵组成的奇偶校验矩阵，并且具有对应于奇偶校验方程的系数的行并分布到相同大小的解码窗口中。 为了增加迭代解码的收敛，除了作为“1”的单个元素之外，与解码窗口相关联的系统矩阵的至少一列的元素是“0”。 数据变量只涉及窗口的一个方程，只要求解窗口的方程就不能解决其他窗口的方程。
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公开(公告)号：US20100064195A1
公开(公告)日：2010-03-11
申请号：US12514590
申请日：2007-11-09
CPC分类号： H03M13/116 , H03M13/1137
摘要： The invention relates to correcting codes for encoding and decoding a data signal. A signal including data variables is coded into a signal including the data variables and parity variables. The encoding and decoding operations are based on a parity check matrix comprised of a systematic matrix and a parity matrix and having rows corresponding coefficients of parity equations and distributed into decoding windows of same size. In order to increase convergence of the iterative decoding, the elements of at least one column of the systematic matrix associated with a decoding window are “0s”, except for a single element which is a “1”. A data variable is only involved in one equation of the window and not involved in solving the equations of other windows as long as the solving of equations of the window is not achieved.
摘要翻译： 本发明涉及用于对数据信号进行编码和解码的代码。 包括数据变量的信号被编码成包括数据变量和奇偶变量的信号。 编码和解码操作基于由系统矩阵和奇偶校验矩阵组成的奇偶校验矩阵，并且具有对应于奇偶校验方程的系数的行并分布到相同大小的解码窗口中。 为了增加迭代解码的收敛，除了作为“1”的单个元素之外，与解码窗口相关联的系统矩阵的至少一列的元素是“0”。 数据变量只涉及窗口的一个方程，只要求解窗口的方程就不能解决其他窗口的方程。
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公开(公告)号：US20090217123A1
公开(公告)日：2009-08-27
申请号：US11988252
申请日：2006-06-30
CPC分类号： H03M13/1194 , H03M13/1105 , H03M13/116 , H03M13/118 , H03M13/1185 , H03M13/2906
摘要： A communication method and a communication system including a first entity (3) including an information source (9) and a coder device (11) connected by a channel (7) transmitting data to a second entity (5) including a decoder device (13), the coder device (11) coding a data sequence sent by the information source (9) to form a set of code words from a parity check matrix including two matrix areas, each matrix area including a processing matrix, a connecting matrix including only one “1” per column and only one “1” per row, and a triangular matrix, and the decoder device (13) decoding a coded reception signal that is received by the second entity and is derived from the set of code words constructed in accordance with said parity check matrix.
摘要翻译： 一种通信方法和通信系统，包括第一实体（3），包括信息源（9）和编码器装置（11），通过信道（7）连接到包括解码器装置（13）的第二实体（5）的信道 ），编码器装置（11）对由信息源（9）发送的数据序列进行编码，以从包括两个矩阵区域的奇偶校验矩阵形成一组码字，每个矩阵区域包括处理矩阵，仅包括连接矩阵 每列一个“1”，每行仅一个“1”，三角矩阵，解码器装置（13）对由第二实体接收的编码的接收信号进行解码，并从构成的代码字集合 根据所述奇偶校验矩阵。
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7.发明授权Device and method with buffer memory, particularly for line/column matrix transposition of data sequences 失效具有缓冲存储器的器件和方法，特别是用于数据序列的线/列矩阵转置
公开(公告)号：US4918527A
公开(公告)日：1990-04-17
申请号：US278678
申请日：1988-12-01
申请人： Pierre Penard , Philippe Quenard
发明人： Pierre Penard , Philippe Quenard
摘要： The device and method disclosed relate to the field of electronic devices and methods enabling the transposition of any even-order square matrix, the elements of which are given in sequence. The goal is to provide for the transposition of sequences of data representing elementary image blocks, without any duplication of the memory space needed to store an elementary block, in optimizing the two parameters of operating speed and space occupied on silicon. This goal is achieved by a buffer memory divided into two identical storage half-planes, working together with a device for the sequencing of the reading/writing operations, providing simultaneously for a reading operation on one of the storage half-planes and a writing operation on the other half-plane.
摘要翻译： 所公开的装置和方法涉及能够转置任何偶数方阵的电子装置和方法领域，其元素依次给出。 目标是提供表示基本图像块的数据序列的转置，而不需要存储基本块所需的存储器空间的重复，来优化硅上占用的操作速度和空间的两个参数。 该目标通过一个被分成两个相同的存储半平面的缓冲存储器实现，与用于读/写操作的顺序的设备一起工作，同时提供一个存储半平面上的读取操作和写入操作 在另一个半平面上
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8.发明授权Random access memory and linear interpolation circuit comprising application thereof 失效随机存取存储器和包括其应用的线性内插电路
公开(公告)号：US4841462A
公开(公告)日：1989-06-20
申请号：US800413
申请日：1985-11-21
IPC分类号： G06F17/17 , G11C8/10 , G11C11/419
CPC分类号： G06F17/17 , G11C11/419 , G11C8/10 , Y10S257/903
摘要： A random access memory (RAM) comprises memory cells each including an RS type flip-flop having complementary data inputs and transistors for forcing the flip-flop by that one of two data wires which is at a given level (high level for example) when a selection wire is at a first given level (high level for example). The flip-flop is connected to an output wire by circuitry for maintaining the output wire at the high level as long as the selection wire is at the first level and for causing the output wire to take the level corresponding to the condition of the flip-flop when the selection wire is brought to the other level. The transistors are preferably N-MOS for higher speed.
摘要翻译： 随机存取存储器（RAM）包括存储单元，每个存储单元包括具有互补数据输入的RS型触发器和晶体管，用于通过位于给定电平（例如高电平）的两条数据线之一强制触发器， 选择线处于第一给定水平（例如，高水平）。 触发器通过电路连接到输出线，用于将输出线保持在高电平，只要选择线处于第一电平并且使输出线获得与触发器的状态相对应的电平， 当选择线被带到另一个水平时翻转。 晶体管优选用于更高速度的N-MOS。
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