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16 条记录 (耗时 0.016 秒)

    Dual connector plate
    3.
    发明授权
    Dual connector plate 失效
    双连接板

    公开(公告)号：US08657630B1

    公开(公告)日：2014-02-25

    申请号：US13468309

    申请日：2012-05-10

    申请人： Eric G. Nelson ,  Boris Radovcic ,  Jeffrey B. Canter ,  George M. Horihan

    发明人： Eric G. Nelson ,  Boris Radovcic ,  Jeffrey B. Canter ,  George M. Horihan

    IPC分类号： H01R25/00 ,  H01R27/02 ,  H01R31/00 ,  H01R33/88

    CPC分类号： H05K7/1445 ,  H01R13/443 ,  H01R13/5219 ,  H01R27/02 ,  H01R31/005

    摘要： A system and method for connecting an advanced electronic module to a legacy chassis is presented. In one embodiment, a connector plate comprises a plate bracket, a module connector, at least two chassis connectors and route logic. The plate bracket has a front side, a back side and an opening. The module connector connects to an electronic module within the opening. The at least two chassis connectors are located on the back side of the bracket plate and are configured to be connected to a legacy chassis or and advanced chassis. The legacy chassis and the advanced chassis do not expect signals from the same number chassis conductors. The routing logic routes signals from the module connector to each of the at least two chassis connectors.

    摘要翻译： 提出了一种用于将高级电子模块连接到传统机箱的系统和方法。 在一个实施例中，连接器板包括板支架，模块连接器，至少两个底盘连接器和路线逻辑。 板支架具有前侧，后侧和开口。 模块连接器连接到开口内的电子模块。 至少两个底盘连接器位于支架板的后侧，并被配置为连接到传统机箱或高级机箱。 传统机箱和高级机箱不要求来自相同编号的机箱导线的信号。 路由逻辑将信号从模块连接器路由到至少两个机架连接器中的每一个。

    MODULAR RADIO COMMUNICATIONS SYSTEMS ARCHITECTURE
    4.
    发明申请
    MODULAR RADIO COMMUNICATIONS SYSTEMS ARCHITECTURE 有权
    模块化无线电通信系统架构

    公开(公告)号：US20120295551A1

    公开(公告)日：2012-11-22

    申请号：US13461888

    申请日：2012-05-02

    申请人： Boris Radovcic ,  Christopher O'Bara

    发明人： Boris Radovcic ,  Christopher O'Bara

    IPC分类号： H04B1/38

    CPC分类号： H04B1/38 ,  G06F13/385

    摘要： An adapter for a communications module includes first terminals for connection with a host interface of a given platform, and second terminals for connection with the communications module. The host interface provides signals associated with the platform and power at corresponding first terminals. The communication module provides associated signals and connections for supplying voltages to the module circuits, at corresponding second terminals. A power converter connected to the first terminals is arranged to output fixed voltages one or more of which is required for the communications module. A power management stage connected to the output of the power converter is arranged to apply the voltages to the second terminals so that the voltages are properly supplied to the module circuits. A buffer stage connected to the first and the second terminals is arranged to buffer or condition shared signals among the host interface and the communications module.

    摘要翻译： 用于通信模块的适配器包括用于与给定平台的主机接口连接的第一终端和用于与通信模块连接的第二终端。 主机接口提供与平台相关联的信号和在相应的第一终端处的功率。 通信模块提供相关联的信号和连接，用于在对应的第二终端向模块电路提供电压。 连接到第一端子的电力转换器被布置成输出通信模块所需的一个或多个固定电压。 连接到功率转换器的输出的电源管理级被布置成将电压施加到第二端子，使得电压被适当地提供给模块电路。 连接到第一和第二终端的缓冲级被布置成在主机接口和通信模块之间缓冲或调节共享信号。

    Personality adapter for modular radio communications systems
    6.
    发明授权
    Personality adapter for modular radio communications systems 有权
    模块化无线电通信系统的个性适配器

    公开(公告)号：US08983375B2

    公开(公告)日：2015-03-17

    申请号：US13461888

    申请日：2012-05-02

    申请人： Boris Radovcic ,  Christopher O'Bara

    发明人： Boris Radovcic ,  Christopher O'Bara

    IPC分类号： H04B5/00 ,  H04B1/38

    CPC分类号： H04B1/38 ,  G06F13/385

    摘要： An adapter for a communications module includes first terminals for connection with a host interface of a given platform, and second terminals for connection with the communications module. The host interface provides signals associated with the platform and power at corresponding first terminals. The communication module provides associated signals and connections for supplying voltages to the module circuits, at corresponding second terminals. A power converter connected to the first terminals is arranged to output fixed voltages one or more of which is required for the communications module. A power management stage connected to the output of the power converter is arranged to apply the voltages to the second terminals so that the voltages are properly supplied to the module circuits. A buffer stage connected to the first and the second terminals is arranged to buffer or condition shared signals among the host interface and the communications module.

    摘要翻译： 用于通信模块的适配器包括用于与给定平台的主机接口连接的第一终端和用于与通信模块连接的第二终端。 主机接口提供与平台相关联的信号和在相应的第一终端处的功率。 通信模块提供相关联的信号和连接，用于在对应的第二终端向模块电路提供电压。 连接到第一端子的电力转换器被布置成输出通信模块所需的一个或多个固定电压。 连接到功率转换器的输出的电源管理级被布置成将电压施加到第二端子，使得电压被适当地提供给模块电路。 连接到第一和第二终端的缓冲级被布置成在主机接口和通信模块之间缓冲或调节共享信号。

    Peek/poke interface on radio system core engine modem to allow debug during system integration
    7.
    发明授权
    Peek/poke interface on radio system core engine modem to allow debug during system integration 有权
    无线电系统核心引擎调制解调器上的Peek / poke接口允许在系统集成期间进行调试

    公开(公告)号：US08843662B2

    公开(公告)日：2014-09-23

    申请号：US13465237

    申请日：2012-05-07

    申请人： Boris Radovcic

    发明人： Boris Radovcic

    IPC分类号： G06F3/00 ,  H03K19/177

    CPC分类号： H03K19/17728

    摘要： A system and method for allowing individual register access during system integration and test is disclosed. A Chip select is routed between an OMAP processor and a waveform FPGA and configured to allow individual register access during system integration and test. Logic is then added to the FPGA to support the single access to the FPGA's peripherals. This allows the user connected to the debug port to be able to send and receive individual commands to and from the waveform FPGA's peripherals. A Graphical User Interface (GUI) maybe developed to provide a graphical interface or scripts may be used to assemble multiple commands thereby increasing flexibility to configure the peripherals during integration and troubleshooting.

    摘要翻译： 公开了一种用于在系统集成和测试期间允许单独寄存器访问的系统和方法。 芯片选择在OMAP处理器和波形FPGA之间布线，并配置为在系统集成和测试期间允许单独的寄存器访问。 逻辑然后被添加到FPGA以支持对FPGA外设的单一访问。 这允许连接到调试端口的用户能够发送和接收来自波形FPGA外设的单独命令。 可能开发图形用户界面（GUI）以提供图形界面或脚本可用于组合多个命令，从而增加在集成和故障排除期间配置外设的灵活性。

    PEEK/POKE INTERFACE ON RADIO SYSTEM CORE ENGINE MODEM TO ALLOW DEBUG DURING SYSTEM INTEGRATION
    8.
    发明申请
    PEEK/POKE INTERFACE ON RADIO SYSTEM CORE ENGINE MODEM TO ALLOW DEBUG DURING SYSTEM INTEGRATION 有权
    无线电系统核心引擎调制解调器上的PEEK / POKE接口在系统集成期间允许调试

    公开(公告)号：US20120290741A1

    公开(公告)日：2012-11-15

    申请号：US13465237

    申请日：2012-05-07

    申请人： Boris Radovcic

    发明人： Boris Radovcic

    IPC分类号： G06F3/00

    CPC分类号： H03K19/17728

    摘要： A system and method for allowing individual register access during system integration and test is disclosed. A Chip select is routed between an OMAP processor and a waveform FPGA and configured to allow individual register access during system integration and test. Logic is then added to the FPGA to support the single access to the FPGA's peripherals. This allows the user connected to the debug port to be able to send and receive individual commands to and from the waveform FPGA's peripherals. A Graphical User Interface (GUI) maybe developed to provide a graphical interface or scripts may be used to assemble multiple commands thereby increasing flexibility to configure the peripherals during integration and troubleshooting.

    摘要翻译： 公开了一种用于在系统集成和测试期间允许单独寄存器访问的系统和方法。 芯片选择在OMAP处理器和波形FPGA之间布线，并配置为在系统集成和测试期间允许单独的寄存器访问。 逻辑然后被添加到FPGA以支持对FPGA外设的单一访问。 这允许连接到调试端口的用户能够发送和接收来自波形FPGA外设的单独命令。 可能开发图形用户界面（GUI）以提供图形界面或脚本可用于组合多个命令，从而增加在集成和故障排除期间配置外设的灵活性。

    Method for emulating low frequency serial clock data recovery RF control bus operation using high frequency data
    9.
    发明授权
    Method for emulating low frequency serial clock data recovery RF control bus operation using high frequency data 失效
    用于模拟低频串行时钟数据恢复的方法使用高频数据的RF控制总线操作

    公开(公告)号：US08780962B2

    公开(公告)日：2014-07-15

    申请号：US13465208

    申请日：2012-05-07

    申请人： James C. Gower ,  Boris Radovcic

    发明人： James C. Gower ,  Boris Radovcic

    IPC分类号： H04B1/38 ,  H04W88/00 ,  H04B1/00

    CPC分类号： H04B1/38 ,  H04B1/0003 ,  H04W88/00

    摘要： A system and method for emulating low frequency RF control bus operation using high frequency data is disclosed. In transmission path, the low frequency RFCB transmit data bytes are encoded and then up-sampled. The up-sampled data is then sent to hardware serializer for transmission. The resulting RF serial output stream appears to the external receiver to be encoded at low frequency even though the transceiver is operating at high frequency. In reception path, RFCB serial input data is de-serialized and then down-sampled. The down sampled data is then passed through custom byte-alignment logic and finally decoded. The transceivers are operated at high frequency but data is decoded and received as if it were at low rate. The FPGA serial transceiver are operated at a high frequency and sends each data bit a plurality of times to create a low effective data rate.

    摘要翻译： 公开了一种使用高频数据模拟低频RF控制总线操作的系统和方法。 在传输路径中，对低频RFCB发送数据字节进行编码，然后进行上采样。 然后将上采样数据发送到硬件串行器进行传输。 即使收发器工作在高频下，得到的RF串行输出流对于外部接收机似乎被以低频编码。 在接收路径中，RFCB串行输入数据被反序列化，然后下采样。 下采样数据然后通过自定义字节对齐逻辑，并最终解码。 收发器以高频率运行，但是数据被解码和接收，就好像它是低速率一样。 FPGA串行收发器以高频率工作，并且多次发送每个数据位以创建低有效数据速率。

    CLOCK DISTRIBUTION ARCHITECTURE FOR DUAL INTEGRATED CORE ENGINE TRANSCEIVER FOR USE IN RADIO SYSTEM
    10.
    发明申请
    CLOCK DISTRIBUTION ARCHITECTURE FOR DUAL INTEGRATED CORE ENGINE TRANSCEIVER FOR USE IN RADIO SYSTEM 有权
    用于无线电系统的双集成核心发射机收发器的时钟分配架构

    公开(公告)号：US20120287977A1

    公开(公告)日：2012-11-15

    申请号：US13465269

    申请日：2012-05-07

    申请人： Boris Radovcic ,  Michael S. Vogas

    发明人： Boris Radovcic ,  Michael S. Vogas

    IPC分类号： H04L7/04 ,  H04B1/38 ,  H04B15/00

    CPC分类号： H04L7/0008

    摘要： A method and apparatus of minimizing corruption of a reference clock to a RF circuitry in a radio system is disclosed. A DICE-T receives a reference clock in a Low Voltage Differential Signal (LVDS) format from a GVA. The DICE-T personality card converts the reference clock signal into an analog signal. The analog signal is supplied to the Core Engine RF card and the LVDS format signal is supplied to the Core Engine modem for local clocking. The Core Engine RF feeds the analog signal into a programmable phase locked loop chip to generate all the clocks required for RF processing. The analog signal is also used to provide the clocks to the ADC and DAC of core engine modem. By routing the reference clock directly to the RF card then deriving the modem clocks, the phase noise of the reference clock is reduced.

    摘要翻译： 公开了一种将参考时钟的损坏最小化到无线电系统中的RF电路的方法和装置。 DICE-T以GVA的低电压差分信号（LVDS）格式接收参考时钟。 DICE-T个性卡将参考时钟信号转换为模拟信号。 模拟信号提供给核心引擎RF卡，并将LVDS格式信号提供给核心引擎调制解调器进行本地时钟。 核心引擎RF将模拟信号馈送到可编程锁相环芯片中，以产生RF处理所需的所有时钟。 模拟信号也用于向核心引擎调制解调器的ADC和DAC提供时钟。 通过将参考时钟直接路由到RF卡，然后导出调制解调器时钟，降低了参考时钟的相位噪声。