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1.发明授权Memory controller having receiver circuitry capable of alternately generating one or more data streams as data is received at a data pad, in response to counts of strobe edges received at a strobe pad 失效存储器控制器具有能够交替地产生一个或多个数据流的接收机电路，作为在数据焊盘处接收数据，响应于在选通焊盘处接收到的选通沿的计数公开(公告)号：US07103793B2
公开(公告)日：2006-09-05
申请号：US10685940
申请日：2003-10-14
CPC分类号： G06F13/1689
摘要： A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1x double data rate memory speed, and means for receiving data and strobe signals via said pads at Mx double data rate memory speed (M2).
摘要翻译： 双数据速率存储器控制器设置有多个数据和选通焊盘，用于经由所述焊盘以1x双倍数据速率存储器速度接收数据和选通信号的装置，以及用于经由所述焊盘以Mx双倍数据接收数据和选通信号的装置 速率记忆速度（M2）。
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公开(公告)号：US06633965B2
公开(公告)日：2003-10-14
申请号：US09828604
申请日：2001-04-07
IPC分类号： G06F1200
CPC分类号： G06F13/1689
摘要： Methods and apparatus for receiving data from memory, the data being associated with a strobe, are disclosed herein. In general, the methods and apparatus provide a memory controller with a means for receiving data at different rates. Data may be received by a memory controller at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, include multiplexers which receive data from two or more banks of memory modules and then multiplex the data into one or more data streams which are then transmitted to the memory controller at twice the rate which the memory modules in either bank could transmit data to the memory controller.
摘要翻译： 本文公开了从存储器接收数据的方法和装置，与选通相关联的数据。 通常，所述方法和装置为存储器控制器提供了以不同速率接收数据的装置。 数据可以由存储器控制器以不同的速率接收，因为例如，存储器控制器用于其直接连接到多个存储器模块的环境中，和/或在其经由多个存储器模块附接到多个存储器模块的环境中使用 中介芯片 中间芯片可以例如包括从两个或多个存储器模块组接收数据的多路复用器，然后将数据复用到一个或多个数据流中，然后将数据流以两倍于存储器模块的速率传输到存储器控制器 银行可以将数据发送到内存控制器。
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3.发明授权Memory controller driver circuitry having a multiplexing stage to provide data to at least N-1 of N data propagation circuits, and having output merging circuitry to alternately couple the N data propagation circuits to a data pad to generate either a 1x or Mx stream of data 有权存储器控制器驱动器电路，具有多路复用级以向N个数据传播电路中的至少N-1提供数据，并且具有输出合并电路，用于将N个数据传播电路交替耦合到数据焊盘，以产生1x或Mx数据流公开(公告)号：US07103790B2
公开(公告)日：2006-09-05
申请号：US10695881
申请日：2003-10-28
CPC分类号： G06F13/1689
摘要： A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1× double data rate memory speed, and means for receiving data and strobe signals via said pads at M× double data rate memory speed (M≧2).
摘要翻译： 双数据速率存储器控制器设置有多个数据和选通焊盘，用于经由所述焊盘以1x双倍数据速率存储器速度接收数据和选通信号的装置，以及用于经由所述焊盘以Mx双倍数据接收数据和选通信号的装置 速率记忆速度（M> = 2）。
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4.发明授权公开(公告)号：US06889335B2
公开(公告)日：2005-05-03
申请号：US09828041
申请日：2001-04-07
CPC分类号： G06F13/1684 , G06F13/4086
摘要： Methods and apparatus are disclosed herein for providing tri-state noise immunity for memory systems such as DDR memory systems, wherein 1) there are large variations in read data loop delay, and 2) strobe buses have similar termination and threshold voltages. In one embodiment, strobe receiver circuitry includes a counter and counter control logic. The counter updates a count in response to strobe edges of received strobe signals. The counter control logic enables the counter before each strobe signal is received by generating control signals asynchronously with respect to the received strobe signals. The counter control logic also resets the counter after each strobe signal is received by receiving feedback from the counter and, in response to the feedback, resetting the counter asynchronously with respect to the received strobe signals. The strobe receiver circuitry may form part of a DDR memory controller.
摘要翻译： 本文公开了用于为诸如DDR存储器系统的存储器系统提供三态噪声抗扰性的方法和装置，其中1）读取数据环路延迟有很大变化，以及2）选通总线具有类似的终止和阈值电压。 在一个实施例中，选通接收机电路包括计数器和计数器控制逻辑。 该计数器响应于所接收的选通信号的选通沿来更新计数。 通过相对于所接收的选通信号异步地产生控制信号，计数器控制逻辑使得在接收每个选通信号之前的计数器。 计数器控制逻辑还通过从计数器接收反馈而接收到每个选通信号之后复位计数器，并且响应于该反馈，相对于所接收的选通信号来异步地重置计数器。 选通接收器电路可以形成DDR存储器控制器的一部分。
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公开(公告)号：US06678811B2
公开(公告)日：2004-01-13
申请号：US09827768
申请日：2001-04-07
IPC分类号： G06F1300
CPC分类号： G06F13/1689
摘要： Methods and apparatus for writing data to memory are disclosed herein. In general, the methods and apparatus provide a memory controller with means for writing data at different rates. Data may need to be written to memory at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, comprise demultiplexers which receive data from the memory controller at twice the rate which data could be written directly to a memory module. The intermediary chip may then simultaneously transmit the demultiplexed write data to memory modules in two or more banks of memory modules.
摘要翻译： 本文公开了将数据写入存储器的方法和装置。 通常，方法和装置为存储器控制器提供以不同速率写入数据的装置。 数据可能需要以不同的速率写入存储器，因为例如，存储器控制器在其直接连接到多个存储器模块的环境中使用，和/或在其经由多个存储器模块附接到多个存储器模块的环境中使用 中介芯片 中间芯片可以例如包括解复用器，其以从该数据可以直接写入存储器模块的速率的两倍来从存储器控制器接收数据。 中间芯片然后可以同时将解复用的写入数据发送到两个或更多个存储器模块组中的存储器模块。
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公开(公告)号：US06625702B2
公开(公告)日：2003-09-23
申请号：US09827766
申请日：2001-04-07
IPC分类号： G06F1200
CPC分类号： G06F13/1678 , G06F12/04
摘要： A memory controller that reads and writes memory modules populated with non-homogeneous data width RAM devices, wherein the RAM devices are of a type which send and receive data with a source synchronous strobe. The memory controller maintains a memory map and stores therein indications of data/strobe ratios which are required to read and write memory modules coupled to the memory controller. The indications of data/strobe ratios are addressed during read and write cycles of the memory controller. Addressed indications are used during write cycles to ensure that strobes are generated at a correct number of strobe pads. Addressed indications are used during read cycles to ensure that received data signals are associated with their correct and corresponding strobe signals.
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7.发明授权Memory controller to communicate with memory devices that are associated with differing data/strobe ratios 失效存储器控制器与与不同数据/选通比率相关联的存储器件通信公开(公告)号：US06990562B2
公开(公告)日：2006-01-24
申请号：US10685929
申请日：2003-10-14
IPC分类号： G06F12/00
CPC分类号： G06F13/1689
摘要： A memory controller is provided with a memory to store indications of data/strobe ratios that are required to access memory devices that are coupled to the memory controller. The memory controller is also provided with a memory interface through which the memory controller initiates data transmissions with the memory devices. For a data transmission initiated with a particular one of the memory devices, the ratio of data signals to strobe signals sent/received through the interface is dynamically determined in response to a corresponding indication of a data/strobe ratio stored in the memory.
摘要翻译： 存储器控制器设置有存储器，用于存储访问耦合到存储器控制器的存储器件所需的数据/选通比率的指示。 存储器控制器还具有存储器接口，存储器控制器通过存储器接口与存储器件发起数据传输。 对于利用特定存储器件发起的数据传输，响应于存储在存储器中的数据/选通比率的对应指示来动态地确定数据信号与通过接口发送/接收的选通信号的比率。
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公开(公告)号：US08959398B2
公开(公告)日：2015-02-17
申请号：US13587631
申请日：2012-08-16
申请人： Scott P. Nixon , Eric M. Rentschler
发明人： Scott P. Nixon , Eric M. Rentschler
IPC分类号： G06F11/00
CPC分类号： G06F11/3656
摘要： An integrated circuit with debug capability includes a first packer and synchronizer to combine a multiple number of values of a first trigger signal received from a first circuit to form a first packed trigger signal and to output a synchronized first packed trigger signal in response to a trigger clock signal, the first trigger signal being synchronous with a first source clock signal, a first logic gate to provide a first output trigger signal indicative of whether any of the first multiple number of values of the first trigger signal in the first synchronized packed trigger signal is in a first state, and a debug state machine responsive to the first output trigger signal to selectively provide a first action signal.
摘要翻译： 具有调试功能的集成电路包括：第一封隔器和同步器，用于组合从第一电路接收的第一触发信号的多个值，以形成第一打包触发信号，并响应触发器输出同步的第一打包触发信号 时钟信号，第一触发信号与第一源时钟信号同步;第一逻辑门，用于提供第一输出触发信号，指示第一同步打包触发信号中第一触发信号的第一多个数值是否为第一触发信号 处于第一状态，并且调试状态机响应于第一输出触发信号选择性地提供第一动作信号。
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公开(公告)号：US5671373A
公开(公告)日：1997-09-23
申请号：US480607
申请日：1995-06-08
摘要： An apparatus and method for transferring data between first and second circuit blocks of a computer graphics system are provided. The first and second circuit blocks are interconnected by a data bus having n bits. The apparatus includes a circuit in the first circuit block for sequentially transmitting data words from the first circuit block to a second circuit block on the data bus. The data words include one or more long data words having more than n bits. The apparatus further includes a register in the first circuit block for storing bits of the long data words in excess of n bits, and a controller in the first circuit block for loading the bits of the long data words in excess of n bits into the register and for combining the bits of the long data words stored in the register into a composite data word for transmission to the second circuit block. The composite data word may include a short data word having less than n bits. In a preferred embodiment, Z coordinate data words having 40 bits are transmitted with an 8 bit command word over a 32 bit data bus without extra bus cycles.
摘要翻译： 提供了一种用于在计算机图形系统的第一和第二电路块之间传送数据的装置和方法。 第一和第二电路块通过具有n位的数据总线相互连接。 该装置包括在第一电路块中用于将数据字从第一电路块顺序发送到数据总线上的第二电路块的电路。 数据字包括具有多于n位的一个或多个长数据字。 该装置还包括：第一电路块中用于存储超过n位的长数据字的位的寄存器;以及第一电路块中的控制器，用于将超过n位的长数据字的位加载到寄存器 并且将存储在寄存器中的长数据字的位组合成用于传输到第二电路块的复合数据字。 复合数据字可以包括具有小于n位的短数据字。 在优选实施例中，具有40位的Z坐标数据字通过32位数据总线以8位命令字发送，而不需要额外的总线周期。
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公开(公告)号：US20140053027A1
公开(公告)日：2014-02-20
申请号：US13587631
申请日：2012-08-16
申请人： Scott P. Nixon , Eric M. Rentschler
发明人： Scott P. Nixon , Eric M. Rentschler
IPC分类号： G06F11/34
CPC分类号： G06F11/3656
摘要： An integrated circuit with debug capability includes a first packer and synchronizer to combine a multiple number of values of a first trigger signal received from a first circuit to form a first packed trigger signal and to output a synchronized first packed trigger signal in response to a trigger clock signal, the first trigger signal being synchronous with a first source clock signal, a first logic gate to provide a first output trigger signal indicative of whether any of the first multiple number of values of the first trigger signal in the first synchronized packed trigger signal is in a first state, and a debug state machine responsive to the first output trigger signal to selectively provide a first action signal.
摘要翻译： 具有调试功能的集成电路包括：第一封隔器和同步器，用于组合从第一电路接收的第一触发信号的多个值以形成第一打包触发信号，并响应触发器输出同步的第一打包触发信号 时钟信号，第一触发信号与第一源时钟信号同步;第一逻辑门，用于提供第一输出触发信号，指示第一同步打包触发信号中第一触发信号的第一多个数值是否为第一触发信号 处于第一状态，并且调试状态机响应于第一输出触发信号选择性地提供第一动作信号。
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