公开(公告)号：US06650163B1

公开(公告)日：2003-11-18

申请号：US10216618

申请日：2002-08-08

申请人： Jeffrey L. Burns ,  Alan James Drake ,  Uttam Shyamalindu Ghoshal ,  Kevin John Nowka

发明人： Jeffrey L. Burns ,  Alan James Drake ,  Uttam Shyamalindu Ghoshal ,  Kevin John Nowka

IPC分类号： H03K300

CPC分类号： H03B5/1212 ,  H03B5/1228 ,  H03K3/354

摘要： A system and integrated circuit (die) including a clock generator that includes an on-chip inductor and uses the inherent capacitance of the load to generate a sinusoidal clock signal. The inductor is connected between a current source and an inverting switch. The output of the switch is a substantially sinusoidal signal that connected directly to at least a portion of the clock driven circuits without intermediate buffering. In the preferred embodiment, the clock generator is a dual phase design that includes a pair of cross-coupled MOSFET's, a pair of solid state on-chip inductors, and a current source. Each of the on-chip inductors is connected between the current source and the drain of one of the MOSFET's. The outputs of the clock generator are provided directly to the clock inputs of at least a portion of the clock driven circuits on the die. In this embodiment, the frequency of the clock generator output signal is predominantly determined by the inductance of the inductive elements and the capacitance of the clock driven circuitry. This design eliminates the need for incorporating distinct capacitor elements in the clock generator itself and produces a clock generator in which a significant portion of the power oscillates between the generator's inductive elements and the capacitive elements of the load thereby reducing the power required to be supplied by the current source.

摘要翻译： 一种包括时钟发生器的系统和集成电路（芯片），其包括片上电感器并且使用负载的固有电容来产生正弦时钟信号。 电感连接在电流源和反相开关之间。 开关的输出是基本上正弦信号，其直接连接到时钟驱动电路的至少一部分而没有中间缓冲。 在优选实施例中，时钟发生器是双相设计，其包括一对交叉耦合MOSFET，一对固态片上电感器和电流源。 每个片上电感器连接在MOSFET之一的电流源和漏极之间。 时钟发生器的输出被直接提供给芯片上至少一部分时钟驱动电路的时钟输入。 在该实施例中，时钟发生器输出信号的频率主要由电感元件的电感和时钟驱动电路的电容决定。 该设计消除了在时钟发生器本身中并入不同的电容器元件并产生时钟发生器的需要，其中大部分功率在发电机的感应元件和负载的电容元件之间振荡，从而减少由 当前来源。

公开(公告)号：US07443195B2

公开(公告)日：2008-10-28

申请号：US10773427

申请日：2004-02-09

申请人： Juan-Antonio Carballo ,  Jeffrey L. Burns ,  Gary Dale Carpenter ,  Kevin John Nowka ,  Ivan Vo ,  Seung-moon Yoo

发明人： Juan-Antonio Carballo ,  Jeffrey L. Burns ,  Gary Dale Carpenter ,  Kevin John Nowka ,  Ivan Vo ,  Seung-moon Yoo

IPC分类号： H03K19/0175 ,  G05F1/10

CPC分类号： H03K19/0008

摘要： A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.

摘要翻译： 提供一种在保持性能特性的同时降低功耗并避免嵌入在SOC中的高速通信链路的昂贵的过度设计的方法。 该方法包括以降低的电压合成通信链路，以确定和隔离与非电源电压关键的电路相关的电源电压关键的电路。 电源电压关键电路包含不降低电压而不降低通信链路性能特性的组件。 使用非降低电压来驱动电源电压关键电路，同时使用降低的电压来驱动非电源电压关键电路。 使用嵌入在通信链路中的电压调节器来产生降低的电压。

公开(公告)号：US6035390A

公开(公告)日：2000-03-07

申请号：US5471

申请日：1998-01-12

申请人： Jeffrey L. Burns ,  Sang Hoo Dhong ,  Kevin John Nowka ,  Joel Abraham Silberman

发明人： Jeffrey L. Burns ,  Sang Hoo Dhong ,  Kevin John Nowka ,  Joel Abraham Silberman

IPC分类号： G06F9/38 ,  G06F7/48 ,  G06F9/302 ,  G06F9/305 ,  G06F9/32 ,  G06F9/30

CPC分类号： G06F9/3001 ,  G06F7/48 ,  G06F9/30094

摘要： A processor includes at least an execution unit that executes an instruction by performing an operation indicated by the instruction utilizing one or more operands and condition code logic that determines less than, greater than, and equal to condition code bits associated with the instruction concurrently with execution of the instruction by the execution unit. In one embodiment, the condition code logic includes a single computation stage that receives as inputs individual bit values of bit positions within first and second operands and logically combines the individual bit values. The single computation stage outputs, for each bit position, propagate, generate, and kill signals that collectively indicate values for the less than, greater than, and equal to condition code bits. One or more merging stages coupled to the computation stage then merge the propagate, generate, and kill signals into output signals that set the condition code bits.

摘要翻译： 处理器至少包括一个执行单元，该执行单元通过使用一个或多个操作数和条件代码逻辑执行指令所指示的操作来执行指令，所述操作数和条件代码逻辑确定小于，大于和等于与执行同时执行的指令相关联的条件代码位 的执行单元的指令。 在一个实施例中，条件码逻辑包括单个计算阶段，其接收第一和第二操作数中的比特位置的各个比特值作为输入，并逻辑地组合各个比特值。 对于每个位位置，单个计算级输出传播，产生和去除共同指示小于，大于和等于条件码位的值的信号。 耦合到计算阶段的一个或多个合并阶段然后将传播，生成和终止信号合并到设置条件码位的输出信号中。

公开(公告)号：US06812739B2

公开(公告)日：2004-11-02

申请号：US10255471

申请日：2002-09-26

申请人： Juan-Antonio Carballo ,  Jeffrey L. Burns ,  Gary Dale Carpenter ,  Kevin John Nowka ,  Ivan Vo ,  Seung-moon Yoo

发明人： Juan-Antonio Carballo ,  Jeffrey L. Burns ,  Gary Dale Carpenter ,  Kevin John Nowka ,  Ivan Vo ,  Seung-moon Yoo

IPC分类号： H03K190175

CPC分类号： H03K19/0008

摘要： A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.

公开(公告)号：US06724221B2

公开(公告)日：2004-04-20

申请号：US10112513

申请日：2002-03-28

申请人： Juan-Antonio Carballo ,  David William Boerstler ,  Jeffrey L. Burns ,  Kevin John Nowka ,  Li Shi

发明人： Juan-Antonio Carballo ,  David William Boerstler ,  Jeffrey L. Burns ,  Kevin John Nowka ,  Li Shi

IPC分类号： H03K1921

CPC分类号： H03K19/215

摘要： In one form of the invention, circuitry having exclusive-OR and latch functionality includes timing circuitry and logic circuitry. The circuitry includes a memory, with first and second memory nodes, for storing a state and its complement, and first and second timing circuitry portions, each operable to receive at least one timing signal, coupled to the respective memory nodes. The logic circuitry includes first and second logic circuitry portions, each of which is operable to receive at least first and second data signals. Each of the logic circuitry portions is coupled in series with a conditionally conductive path of one of the respective first and second timing circuitry portions.

摘要翻译： 在本发明的一种形式中，具有异或和锁存功能的电路包括定时电路和逻辑电路。 电路包括具有用于存储状态及其补码的第一和第二存储器节点的存储器，以及第一和第二定时电路部分，每个定时电路部分可操作以接收耦合到相应存储器节点的至少一个定时信号。 逻辑电路包括第一和第二逻辑电路部分，每个逻辑电路部分可操作以接收至少第一和第二数据信号。 每个逻辑电路部分与相应的第一和第二定时电路部分之一的条件导电路径串联耦合。

公开(公告)号：US06570408B2

公开(公告)日：2003-05-27

申请号：US09931304

申请日：2001-08-16

申请人： Kevin John Nowka

发明人： Kevin John Nowka

IPC分类号： H03K19096

CPC分类号： H03K19/0019

摘要： In one aspect, a method for charge recovery in dynamic circuitry includes discharging a dynamic node during an evaluation interval by input circuitry coupled to the dynamic node responsive to one or more input signals. The discharging includes transferring the charge from the dynamic node to a capacitor during the evaluation time interval. The dynamic node is charged during a precharge interval by a voltage source and precharge timing circuitry coupled to the dynamic node responsive to a precharge signal. The charging includes transferring the charge from the capacitor back to the dynamic node.

摘要翻译： 一方面，一种用于动态电路中的电荷恢复的方法包括：响应于一个或多个输入信号，通过耦合到动态节点的输入电路在评估间隔期间对动态节点进行放电。 放电包括在评估时间间隔期间将电荷从动态节点转移到电容器。 动态节点在预充电间隔期间被电压源充电，并且响应于预充电信号耦合到动态节点的预充电定时电路。 充电包括将电荷从电容器转移回动态节点。

公开(公告)号：US06445217B1

公开(公告)日：2002-09-03

申请号：US09810026

申请日：2001-03-15

申请人： Nobuo Kojima ,  Kevin John Nowka ,  Huajun Wen

发明人： Nobuo Kojima ,  Kevin John Nowka ,  Huajun Wen

IPC分类号： H03F345

CPC分类号： H03K3/356156 ,  H03K3/037

摘要： An edge-triggered latch that incorporates pass-transistor logic (PTL) in the data and clock generation paths. In accordance with one embodiment, an edge-triggered latch includes a data input and at least one data path PTL transistor that passes data from the data input into a storage node in response to a latch trigger signal. A latch trigger circuit generates the latch-trigger signal in response to a clock signal transition.

摘要翻译： 在数据和时钟产生路径中集成了通过晶体管逻辑（PTL）的边沿触发锁存器。 根据一个实施例，边缘触发锁存器包括数据输入和至少一个数据通路PTL晶体管，其响应于锁存触发信号将数据从输入到存储节点的数据传送。 锁存触发电路响应时钟信号转换产生锁存触发信号。

公开(公告)号：US06441667B1

公开(公告)日：2002-08-27

申请号：US09820460

申请日：2001-03-29

申请人： David William Boerstler ,  Robert Keven Montoye ,  Kevin John Nowka

发明人： David William Boerstler ,  Robert Keven Montoye ,  Kevin John Nowka

IPC分类号： G06F104

CPC分类号： H03L7/087 ,  G06F1/04 ,  H03L7/091 ,  H03L7/0995 ,  Y10S331/02

摘要： The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate a control voltage which controls the frequency of the MVCO and to-generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.

摘要翻译： 同步状态输出与多相输出组合使用以产生和误差信号，该信号可用于产生控制电压，该控制电压控制MVCO的频率并产生移位的时钟，该时钟被分成顺序电路以产生 具有频率F的正交时钟

公开(公告)号：US06405231B1

公开(公告)日：2002-06-11

申请号：US09282270

申请日：1999-03-31

申请人： Kevin John Nowka

发明人： Kevin John Nowka

IPC分类号： G06F738

CPC分类号： G06F7/49957

摘要： An apparatus for rounding intermediate normalized mantissas within a floating-point processor is disclosed. The apparatus for rounding intermediate normalized mantissas within a floating-point processor includes an AND circuit, a selection circuit, and a multiplexor. The AND circuit generates an AND signal and its complement from a normalized mantissa. The selection circuit generates a select_AND signal and its complement from the normalized mantissa. The multiplexor, which is coupled to the AND circuit and the selection circuit, chooses either the AND signal or its complement signal as a rounded normalized mantissa according to the select_AND signal and its complement signal from the selection circuit.

摘要翻译： 公开了一种用于在浮点处理器内舍入中间标准化尾数的装置。 用于对浮点处理器内的中间归一化尾数进行舍入的装置包括与电路，选择电路和多路复用器。 “与”电路从标准化尾数生成一个“与”信号及其补码。 选择电路从标准化尾数生成一个select_AND信号及其补码。 耦合到AND电路和选择电路的多路复用器根据来自选择电路的select_AND信号及其补码信号，选择AND信号或其补码信号作为舍入的归一化尾数。

公开(公告)号：US08010066B2

公开(公告)日：2011-08-30

申请号：US12024448

申请日：2008-02-01

申请人： Juan-Antonio Carballo ,  Kevin John Nowka ,  Ivan Vo ,  Seung-moon Yoo

发明人： Juan-Antonio Carballo ,  Kevin John Nowka ,  Ivan Vo ,  Seung-moon Yoo

IPC分类号： H04B1/04

CPC分类号： H04L25/028 ,  H04L25/0272 ,  H04L25/0292

摘要： A digital transmission circuit and interface provide selectable power consumption via multiple weighted driver slices, improving the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

摘要翻译： 数字传输电路和接口通过多个加权驱动器片提供可选择的功耗，提高接口的灵活性，同时在可能的同时降低发射机功耗，面积和复杂性。 级联的一系列驱动器级由一组并行片提供，并且控制逻辑激活一个或多个片，其组合以产生级联的有源驱动器电路。 切片组合的功耗/驱动器级别可选性提供了可以针对特定应用进行微调的驱动器，以在最小功耗级别提供所需的性能。