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1.发明授权Integrated circuit with in situ circuit arrangement for testing integrity of differential receiver inputs 有权具有原位电路装置的集成电路，用于测试差分接收器输入的完整性公开(公告)号：US06407569B1
公开(公告)日：2002-06-18
申请号：US09275295
申请日：1999-03-24
申请人： Jeffrey Paul Boettler , Robert Glen Gerowitz , William Arthur Noon , Howard James Schubert, Jr. , Chad Everett Winemiller
发明人： Jeffrey Paul Boettler , Robert Glen Gerowitz , William Arthur Noon , Howard James Schubert, Jr. , Chad Everett Winemiller
IPC分类号： G01R3128
CPC分类号： G01R31/318572 , G01R31/31926
摘要： Stuck-at fault, shorted and open circuit conditions occurring in the differential inputs to Differential Receivers on a Large Scale Integrated (LSI) chip are detected by a test circuit arrangement fabricated on the chip. The test circuit arrangement includes Pass Gate devices operatively coupled to the differential inputs and an Exclusive NOR circuit (XNOR) coupled to the Pass Gate devices. Pull devices are coupled to the Pass Gate devices and the differential inputs. By activating the Pass Gate devices and applying a test sequence to the differential inputs, the state of the output of the XNOR circuit indicates if an open circuit, stuck-at or short exists in the inputs to the Differential Receiver.
摘要翻译： 在大规模集成（LSI）芯片上的差分接收器的差分输入中出现的故障，短路和开路状况由芯片上制造的测试电路布置检测。 测试电路装置包括可操作地耦合到差分输入的通过栅极器件和耦合到通过栅极器件的异或异或电路（XNOR）。 拉动装置耦合到通过门装置和差分输入。 通过激活Pass Gate器件并将测试序列应用于差分输入，XNOR电路的输出状态指示差分接收器的输入中是否存在开路，卡住或短路。
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2.发明申请Automated Method for Validating Manufacturing Test Rules Pertaining to an Electronic Component 有权用于验证与电子部件有关的制造测试规则的自动化方法公开(公告)号：US20100042396A1
公开(公告)日：2010-02-18
申请号：US12191538
申请日：2008-08-14
IPC分类号： G06G7/62
CPC分类号： G06F11/263 , G06F11/261
摘要： The invention is generally directed to a method and apparatus for validating a specified manufacturing test rule, which pertains to an electronic component. One embodiment comprising a method includes the step of generating a file of test data sets, wherein each test data set in the file is valid for the rule. Each test data set includes a stimulus comprising one or more single input vectors, and further includes a set of results that are expected, when the stimulus is applied to the electronic component. The method further comprises constructing a testbench to prepare each of a plurality of testcases for simulation, wherein each testcase corresponds to the stimulus and the expected output results of one of the test data sets, and each testcase is disposed to be simulated separately, or independently, from every other testcase. The method further comprises selectively preparing each of the testcases for simulation, in order to provide simulated results for the stimulus corresponding to each testcase. The expected results and the simulated results are compared for each testcase, in order to determine whether there are any differences therebetween. Each of the above steps can be carried out using means that are completely automated. Thus, the entire method for validating manufacturing test rules can likewise be completely automated. Also, the processing applied to different test cases can occur simultaneously or in parallel, to substantially reduce the processing burden.
摘要翻译： 本发明一般涉及用于验证与电子部件有关的特定制造测试规则的方法和装置。 包括方法的一个实施例包括生成测试数据集的文件的步骤，其中文件中设置的每个测试数据对于该规则是有效的。 每个测试数据集包括包括一个或多个单个输入向量的刺激，并且还包括当将刺激应用于电子部件时预期的一组结果。 该方法还包括构建测试台以准备用于模拟的多个测试箱中的每一个，其中每个测试用例对应于一个测试数据组的刺激和预期输出结果，并且每个测试用例被设置为单独模拟或独立地模拟 ，从每个其他测试用例。 该方法还包括选择性地准备每个用于模拟的测试箱，以便提供对应于每个测试箱的刺激的模拟结果。 对每个测试用例比较预期结果和模拟结果，以确定它们之间是否存在差异。 可以使用完全自动化的装置来执行上述步骤中的每一个。 因此，用于验证制造测试规则的整个方法同样可以完全自动化。 此外，应用于不同测试用例的处理可以同时或并行地发生，从而大大减少处理负担。
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公开(公告)号：US08136059B2
公开(公告)日：2012-03-13
申请号：US12257610
申请日：2008-10-24
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Illustrative embodiments provide a computer-implemented method for resolving indeterminate states by inserting logic into a design. The computer-implemented method receives an original design input from a requester to form a received input and determines whether the received input contains an indeterminate output. Responsive to a determination that the received input contains an indeterminate output, the computer-implemented method generates a temporary design from the received input, wherein the temporary design contains “unique” output and all inputs, updates the temporary design, and synthesizes the original design and each temporary design individually to form a synthesized original design and a set of synthesized temporary designs. The computer-implemented method merges the synthesized original design with the set of synthesized temporary design to form a final design; and returns the final design to the requester.
摘要翻译： 说明性实施例提供了一种用于通过将逻辑插入到设计中来解决不确定状态的计算机实现的方法。 计算机实现的方法从请求者接收原始设计输入以形成接收到的输入，并确定接收的输入是否包含不确定的输出。 响应于确定接收到的输入包含不确定的输出，计算机实现的方法从接收到的输入生成临时设计，其中临时设计包含“唯一”输出和所有输入，更新临时设计，并且合成原始设计 和每个临时设计单独形成合成的原始设计和一组合成的临时设计。 计算机实现的方法将合成原始设计与合成临时设计集合合并形成最终设计; 并将最终设计返回给请求者。
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4.发明授权公开(公告)号：US08135571B2
公开(公告)日：2012-03-13
申请号：US12191538
申请日：2008-08-14
CPC分类号： G06F11/263 , G06F11/261
摘要： The invention is directed to validating a specified manufacturing test rule, which pertains to an electronic component. The method includes generating a file of test data sets, wherein each test data set in the file is valid for the rule. Each test data set includes a stimulus comprising one or more single input vectors, and further includes a set of results that are expected. The method further comprises constructing a testbench to prepare testcases for simulation, wherein each testcase corresponds to the stimulus and the expected output results of one of the test data sets, and each testcase is disposed to be simulated separately, or independently, from every other testcase. The method further comprises selectively preparing each of the testcases for simulation, in order to provide simulated results for the stimulus corresponding to each testcase. The expected results and the simulated results are compared for each testcase.
摘要翻译： 本发明旨在验证涉及电子部件的指定制造测试规则。 该方法包括生成测试数据集的文件，其中文件中设置的每个测试数据对于该规则是有效的。 每个测试数据集包括包括一个或多个单个输入向量的刺激，并且还包括预期的一组结果。 该方法还包括构建测试台以准备用于模拟的测试用例，其中每个测试用例对应于一个测试数据组的激励和预期输出结果，并且每个测试用例被设置为单独地或独立地从每个其他测试用例模拟 。 该方法还包括选择性地准备每个用于模拟的测试箱，以便提供对应于每个测试箱的刺激的模拟结果。 对每个测试用例比较预期结果和模拟结果。
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5.发明授权Automatically creating manufacturing test rules pertaining to an electronic component 有权自动创建与电子元件相关的制造测试规则公开(公告)号：US08065641B2
公开(公告)日：2011-11-22
申请号：US12203038
申请日：2008-09-02
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A system for creating manufacturing test rules. Stimuli for an electronic design are generated automatically by a stimuli generator. The stimuli generator takes into account certain limitations of the design when automatically generating the manufacturing test rules. The design is tested by a testbench using the stimuli. A simulation log for the design is generated by the testbench. The simulation log is then processed by a simulation log processor. An HDL representation of the design is generated by the simulation log processor using the processed simulation log. A gate-level version of the design is generated by a synthesis tool using the HDL representation of the design. The gate-level version of the design is further processed by the synthesis tool to make any necessary modifications. Then, the gate-level version of the design is outputted as the final manufacturing test rule. Thus, creating manufacturing test rules can be completely automated.
摘要翻译： 用于创建制造测试规则的系统。 电子设计的刺激是由刺激发生器自动产生的。 当自动生成制造测试规则时，刺激发生器考虑到设计的某些限制。 该设计由使用刺激的测试台进行测试。 该设计的仿真日志由测试平台生成。 仿真日志由仿真日志处理器处理。 设计的HDL表示由仿真日志处理器使用处理的仿真日志生成。 设计的门级版本由使用设计的HDL表示的综合工具生成。 设计的门级版本由综合工具进一步处理，以进行任何必要的修改。 然后，设计的门级版本作为最终制造测试规则输出。 因此，创建制造测试规则可以完全自动化。
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公开(公告)号：US20100107129A1
公开(公告)日：2010-04-29
申请号：US12257610
申请日：2008-10-24
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Illustrative embodiments provide a computer-implemented method for resolving indeterminate states by inserting logic into a design. The computer-implemented method receives an original design input from a requester to form a received input and determines whether the received input contains an indeterminate output. Responsive to a determination that the received input contains an indeterminate output, the computer-implemented method generates a temporary design from the received input, wherein the temporary design contains “unique” output and all inputs, updates the temporary design, and synthesizes the original design and each temporary design individually to form a synthesized original design and a set of synthesized temporary designs. The computer-implemented method merges the synthesized original design with the set of synthesized temporary design to form a final design; and returns the final design to the requester.
摘要翻译： 说明性实施例提供了一种用于通过将逻辑插入到设计中来解决不确定状态的计算机实现的方法。 计算机实现的方法从请求者接收原始设计输入以形成接收到的输入，并确定接收的输入是否包含不确定的输出。 响应于确定接收到的输入包含不确定的输出，计算机实现的方法从接收到的输入生成临时设计，其中临时设计包含“唯一”输出和所有输入，更新临时设计，并且合成原始设计 和每个临时设计单独形成合成的原始设计和一组合成的临时设计。 计算机实现的方法将合成原始设计与合成临时设计集合合并形成最终设计; 并将最终设计返回给请求者。
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7.发明申请公开(公告)号：US20100057425A1
公开(公告)日：2010-03-04
申请号：US12203038
申请日：2008-09-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A system for creating manufacturing test rules. Stimuli for an electronic design are generated automatically by a stimuli generator. The stimuli generator takes into account certain limitations of the design when automatically generating the manufacturing test rules. The design is tested by a testbench using the stimuli. A simulation log for the design is generated by the testbench. The simulation log is then processed by a simulation log processor. An HDL representation of the design is generated by the simulation log processor using the processed simulation log. A gate-level version of the design is generated by a synthesis tool using the HDL representation of the design. The gate-level version of the design is further processed by the synthesis tool to make any necessary modifications. Then, the gate-level version of the design is outputted as the final manufacturing test rule. Thus, creating manufacturing test rules can be completely automated.
摘要翻译： 用于创建制造测试规则的系统。 电子设计的刺激是由刺激发生器自动产生的。 当自动生成制造测试规则时，刺激发生器考虑到设计的某些限制。 该设计由使用刺激的测试台进行测试。 该设计的仿真日志由测试平台生成。 仿真日志由仿真日志处理器处理。 设计的HDL表示由仿真日志处理器使用处理的仿真日志生成。 设计的门级版本由使用设计的HDL表示的综合工具生成。 设计的门级版本由综合工具进一步处理，以进行任何必要的修改。 然后，设计的门级版本作为最终制造测试规则输出。 因此，创建制造测试规则可以完全自动化。
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8.发明授权Methods, systems and media for managing functional verification of a parameterizable design 有权用于管理可参数设计的功能验证的方法，系统和媒体公开(公告)号：US07237210B2
公开(公告)日：2007-06-26
申请号：US11053220
申请日：2005-02-08
申请人： Robert Brian Likovich, Jr. , Joseph David Mendenhall , John Christopher Morris , David Otero , Chad Everett Winemiller
发明人： Robert Brian Likovich, Jr. , Joseph David Mendenhall , John Christopher Morris , David Otero , Chad Everett Winemiller
CPC分类号： G01R31/318314
摘要： Methods, systems, and media for managing functional verification of a parameterizable design are disclosed. Embodiments include a system having a testbench configuration module adapted to configure a testbench, the testbench having testbench signals and one or more instantiated components having a plurality of ports of a generic design, where the testbench signals are wired to the plurality of ports. The testbench may also have one or more instantiated special components based on chip-specific versions of the design where the special components are wired to the same ports as the generic design. The system may also include a functional verification manager that, through a component module, observes values in the testbench and automatically configure a verification environment based on the observed values, including automatic insertion of checkers at different levels of hierarchy. The testbench may be a VHDL or Verilog testbench in some embodiments.
摘要翻译： 公开了用于管理可参数化设计的功能验证的方法，系统和媒体。 实施例包括具有测试台配置模块的系统，该测试台配置模块适于配置测试台，测试台具有测试台信号，以及具有多个通用设计端口的一个或多个实例组件，其中测试台信号被连接到多个端口。 测试台还可以具有基于芯片特定版本的设计的一个或多个实例化的特殊组件，其中特殊组件被连接到与通用设计相同的端口。 该系统还可以包括功能验证管理器，其通过组件模块观察测试台中的值并且基于所观察到的值自动配置验证环境，包括在不同层次结构中自动插入检查器。 在一些实施例中，测试台可以是VHDL或Verilog测试台。
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9.发明授权Methods, systems and media for functional simulation of noise and distortion on an I/O bus 有权在I / O总线上进行噪声和失真功能仿真的方法，系统和媒体公开(公告)号：US07246332B2
公开(公告)日：2007-07-17
申请号：US11053078
申请日：2005-02-08
申请人： Robert Brian Likovich, Jr. , Joseph David Mendenhall , John Christopher Morris , Robert James Reese , Chad Everett Winemiller
发明人： Robert Brian Likovich, Jr. , Joseph David Mendenhall , John Christopher Morris , Robert James Reese , Chad Everett Winemiller
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Methods, systems, and media for functional simulation of an I/O bus are disclosed. More particularly, a method of simulating distortion and noise parameters of an I/O bus is disclosed. Embodiments include constraining one or more fields of a record and determining delay amounts based on the resulting parameters, where the final delay amount includes a delay buffer and a net of delay amounts associated with the parameters. Embodiments may also include determining a value of a next bit to be sent to the I/O bus and, after waiting the delay amount, driving the bit on the bus to the next bit value. Parameters may include skew, jitter, duty cycle distortion, voltage reference distortion, and drift of any of these parameters. Further embodiments may include signaling the end of a phase in response to a phase done condition being satisfied.
摘要翻译： 公开了用于I / O总线的功能仿真的方法，系统和媒体。 更具体地，公开了一种模拟I / O总线的失真和噪声参数的方法。 实施例包括约束记录的一个或多个字段并且基于所得到的参数来确定延迟量，其中最终延迟量包括延迟缓冲器和与参数相关联的延迟量的净值。 实施例还可以包括确定要发送到I / O总线的下一位的值，并且在等待延迟量之后，将总线上的位驱动到下一个位值。 参数可能包括这些参数中的任何一个的偏移，抖动，占空比失真，电压参考失真和漂移。 另外的实施例可以包括响应于满足相位完成条件来发信号通知相位的结束。
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10.发明授权System and method to independently verify the execution rate of individual tasks by a device via simulation 失效系统和方法通过仿真独立地验证设备执行单个任务的执行率公开(公告)号：US06816829B1
公开(公告)日：2004-11-09
申请号：US09477163
申请日：2000-01-04
申请人： Robert Franklin Clark , Robert Brian Likovich, Jr. , Darryl Jonathan Rumph , Chad Everett Winemiller
发明人： Robert Franklin Clark , Robert Brian Likovich, Jr. , Darryl Jonathan Rumph , Chad Everett Winemiller
IPC分类号： G06F1310
CPC分类号： G06F17/5022
摘要： The present invention describes a system and method for independently verifying the Execution Rate of individual tasks by a device through simulation. Described is a situation in which a system has a main device through which data flows to and from other devices. Bus transfers must fall within required rates. A simulation of the configuration utilizes models of the various devices, including the “Main device”. This simulation is used to verify the data traffic and associated transfer rates. Data transfer includes random bursts, with randomly chosen periods between bursts. The data rate and data validity are measured during each burst period.
摘要翻译： 本发明描述了一种通过仿真独立地验证设备执行速率的系统和方法。 描述了一种系统具有数据流向其他设备的主设备的情况。 巴士转车必须在所需费率之内。 该配置的模拟利用了各种设备的模型，包括“主设备”。 该模拟用于验证数据流量和相关传输速率。 数据传输包括随机突发，随机选择的脉冲间隔。 数据速率和数据有效性在每个脉冲串周期内被测量。
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