公开(公告)号：US08611148B2

公开(公告)日：2013-12-17

申请号：US13428305

申请日：2012-03-23

申请人： Deepanshu Dutta ,  Jeffrey W Lutze ,  Grishma Shah

发明人： Deepanshu Dutta ,  Jeffrey W Lutze ,  Grishma Shah

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427

摘要： In a programming operation, selected storage elements on a selected word line are programmed while unselected storage elements on the selected word line are inhibited from programming by channel boosting. To provide a sufficient but not excessive level of boosting, the amount of boosting can be set based on a data state of the unselected storage element. A greater amount of boosting can be provided for a lower data state which represents a lower threshold voltage and hence is more vulnerable to program disturb. A common boosting scheme can be used for groups of multiple data states. The amount of boosting can be set by adjusting the timing and magnitude of voltages used for a channel pre-charge operation and for pass voltages which are applied to word lines. In one approach, stepped pass voltages on unselected word lines can be used to adjust boosting for channels with selected data states.

公开(公告)号：US20120250418A1

公开(公告)日：2012-10-04

申请号：US13523366

申请日：2012-06-14

申请人： Deepanshu Dutta ,  Jeffrey W Lutze

发明人： Deepanshu Dutta ,  Jeffrey W Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

摘要： In a non-volatile memory system, a multi-phase programming operation is performed in which a drain-side select gate voltage (Vsgd) can be adjusted in different programming phases to accommodate different bit line bias (Vbl) levels. A higher Vbl can be used when Vsgd is higher to avoid unnecessary stress on the SGD transistor and reduce power consumption. For example, Vsgd can be higher in an earlier program phase than in a later program phase. The higher Vbl, which is not based on programming speed, can be is applied when the Vth of a storage element is between lower and upper verify levels of target data states, or throughout a programming phase, or at other times. The higher Vbl is an additional slow down measure which can be implemented in addition to a programming speed-based slow down measure such as a further raised Vbl which is applied to faster-programming storage elements.

摘要翻译： 在非易失性存储器系统中，执行多相编程操作，其中可以在不同的编程阶段调整漏极侧选择栅极电压（Vsgd）以适应不同的位线偏置（Vbl）电平。 当Vsgd较高时可以使用更高的Vbl，以避免SGD晶体管上的不必要的应力，并降低功耗。 例如，Vsgd可能在较早的程序阶段比在较后的程序阶段更高。 当存储元件的Vth在目标数据状态的下限和上限验证电平之间，或者在整个编程阶段，或者在其他时间时，可以应用不基于编程速度的较高Vbl。 较高的Vbl是一种额外的减速措施，除了基于速度的编程速度减慢措施之外，还可以实现这一措施，例如进一步升高的Vbl，其应用于更快编程的存储元件。

公开(公告)号：US08451667B2

公开(公告)日：2013-05-28

申请号：US13360103

申请日：2012-01-27

申请人： Jeffrey W Lutze ,  Deepanshu Dutta

发明人： Jeffrey W Lutze ,  Deepanshu Dutta

IPC分类号： G11C7/00

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： A non-volatile storage system reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. Alternate pairs of adjacent bit lines are grouped into first and second sets. Non-volatile storage elements of the first set of pairs are subject to program pulses and verify operations in each of a first number of iterations, after which non-volatile storage elements of the second set of pairs is subject to program pulses and verify operations in each of a second number of iterations.

摘要翻译： 非易失性存储系统通过使用选择的位线模式进行编程来减少一组非易失性存储元件中的程序干扰，这增加了禁止信道的钳位升压电位以避免程序干扰。 交替的相邻位线对被分组成第一和第二组。 第一组对的非易失性存储元件经受编程脉冲并且在第一迭代次数中的每一个中验证操作，之后第二组对的非易失性存储元件经受编程脉冲并且验证操作 每次迭代次数为次。

公开(公告)号：US08542535B2

公开(公告)日：2013-09-24

申请号：US13181750

申请日：2011-07-13

申请人： Deepanshu Dutta ,  Jeffrey W Lutze

发明人： Deepanshu Dutta ,  Jeffrey W Lutze

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/0483

摘要： A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are driven at levels to optimize endurance. In one approach, the select gates are driven at specific levels throughout an erase operation, in concert with the p-well voltage.

摘要翻译： 擦除非易失性存储器的技术将p阱电压施加到衬底并驱动选择栅极电压以精确地控制选择栅极电压以提高写入擦除耐久性。 NAND串的源极和漏极侧选择栅极被驱动，以优化耐久性。 在一种方法中，与p阱电压一致，在擦除操作期间以特定电平驱动选择栅极。

公开(公告)号：US08537611B2

公开(公告)日：2013-09-17

申请号：US13523366

申请日：2012-06-14

申请人： Deepanshu Dutta ,  Jeffrey W Lutze

发明人： Deepanshu Dutta ,  Jeffrey W Lutze

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

摘要： In a non-volatile memory system, a multi-phase programming operation is performed. In one phase, faster-programming storage elements have a higher bit line bias (Vbl) than slower-programming storage elements. In a next phase, the faster- and slower-programming storage elements have a lower Vbl. Further, a drain-side select gate voltage (Vsgd) can be adjusted in the different programming phases to accommodate the different Vbl levels. A higher Vsgd can be used in the one phase when Vbl is higher to avoid unnecessary stress on the SGD transistor and reduce power consumption. Vsgd can be reduced in the next phase when the lower Vbl is used. The higher Vbl is a slowdown measure which can be applied when the Vth of a storage element is between lower and upper verify levels of target data states, or throughout a programming phase.

摘要翻译： 在非易失性存储器系统中，执行多相编程操作。 在一个阶段，更快编程的存储元件比较慢的编程存储元件具有更高的位线偏置（Vbl）。 在下一阶段，更快和更慢编程的存储元件具有较低的Vbl。 此外，可以在不同的编程阶段调整漏极侧选择栅极电压（Vsgd）以适应不同的Vbl电平。 当Vbl较高以避免SGD晶体管上的不必要的应力并降低功耗时，可以在一相中使用较高的Vsgd。 当使用较低的Vbl时，Vsgd可以在下一个阶段减少。 较高的Vbl是当存储元件的Vth位于目标数据状态的下限和上限验证电平之间或整个编程阶段时可以应用的减速措施。

公开(公告)号：US07839687B2

公开(公告)日：2010-11-23

申请号：US12252727

申请日：2008-10-16

申请人： Deepanshu Dutta ,  Jeffrey W Lutze

发明人： Deepanshu Dutta ,  Jeffrey W Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5648

摘要： A multiple pass programming scheme is optimized using capacitive coupling in the word line to word line direction during program-verify operations. A different pass voltage is used in different programming passes on an adjacent word line of a selected word line which is being verified. In particular, a lower pass voltage can be used in a first pass than in a second pass. The programming process may involve a word line look ahead or zigzag sequence in which WLn is programmed in a first pass, followed by WLn+1 in a first pass, followed by WLn in a second pass, followed by WLn+1 in a second pass. An initial programming pass may be performed before the first pass in which storage elements are programmed to an intermediate state and/or to a highest state.

摘要翻译： 在编程验证操作期间，使用字线到字线方向的电容耦合来优化多通道编程方案。 在正在验证的所选字线的相邻字线上的不同编程遍中使用不同的通过电压。 特别地，可以在第一遍中比在第二遍中使用较低通过电压。 编程过程可以包括字线前视或之字形序列，其中WLn在第一遍中编程，其次是第一遍中的WLn + 1，之后是第二遍中的WLn，之后是第二遍中的WLn + 1 。 可以在其中存储元件被编程到中间状态和/或最高状态的第一遍之前执行初始编程遍。

公开(公告)号：US07606074B2

公开(公告)日：2009-10-20

申请号：US12242831

申请日：2008-09-30

申请人： Jun Wan ,  Jeffrey W Lutze ,  Chan-Sui Pang

发明人： Jun Wan ,  Jeffrey W Lutze ,  Chan-Sui Pang

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3468

摘要： Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select gates. A compensation voltage can be applied to one or more memory cells to substantially normalize the erase behavior of the memory cells. A compensation voltage can be applied to end memory cells of a NAND string to equalize their erase behavior with interior memory cells of the NAND string. A compensation voltage can also be applied to interior memory cells to equalize their erase behavior with end memory cells. Additionally, a compensation voltage can be applied to one or more select gates of a NAND string to compensate for voltages coupled to one or more memory cells from the select gate(s). Various compensation voltages can be used.

摘要翻译： 在擦除操作期间，补偿电压施加到非易失性存储器系统以均衡存储器单元的擦除行为。 补偿电压可以补偿与其他存储器单元和/或选择栅极的NAND串的存储器单元电容耦合的电压。 补偿电压可以施加到一个或多个存储器单元，以基本上规范化存储器单元的擦除行为。 可以将补偿电压施加到NAND串的末端存储单元，以使其与NAND串的内部存储单元的擦除行为相等。 还可以将补偿电压施加到内部存储器单元，以使其与端部存储器单元的擦除行为相等。 此外，补偿电压可以施加到NAND串的一个或多个选择栅极，以补偿耦合到来自选择栅极的一个或多个存储器单元的电压。 可以使用各种补偿电压。

公开(公告)号：US08014209B2

公开(公告)日：2011-09-06

申请号：US12167135

申请日：2008-07-02

申请人： Jeffrey W Lutze ,  Yan Li

发明人： Jeffrey W Lutze ,  Yan Li

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/3404 ,  G11C16/3418

摘要： A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements that were supposed to remain erased, without intentionally erasing programmed data.

摘要翻译： 非易失性存储系统对多个非易失性存储元件执行编程，并且有选择地执行应该保持擦除的非易失性存储元件的至少一个子集的重新擦除，而无需有意地擦除编程数据。

公开(公告)号：US07852683B2

公开(公告)日：2010-12-14

申请号：US12167128

申请日：2008-07-02

申请人： Jeffrey W Lutze ,  Yan Li

发明人： Jeffrey W Lutze ,  Yan Li

IPC分类号： G11C16/04

CPC分类号： G11C16/3404 ,  G11C11/5635 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3413 ,  G11C16/3463

摘要： A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control line).

摘要翻译： 非易失性存储系统通过在连接到公共字线（或其他类型的控制线）的非易失性存储元件的子集上选择性地执行一个或多个擦除操作来校正编程的存储器单元。

公开(公告)号：US07965554B2

公开(公告)日：2011-06-21

申请号：US12167124

申请日：2008-07-02

申请人： Jeffrey W Lutze ,  Yan Li

发明人： Jeffrey W Lutze ,  Yan Li

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/3404 ,  G11C16/3418

摘要： A non-volatile storage system can selectively perform one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control line) without intentionally erasing other non-volatile storage elements that are connected to the common word line (or other type of control line) but not in the subset.

摘要翻译： 非易失性存储系统可以选择性地对连接到公共字线（或其他类型的控制线）的非易失性存储元件的子集执行一个或多个擦除操作，而不会有意地擦除其他非易失性存储元件 连接到公共字线（或其他类型的控制线），但不在子集中。