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1.发明授权
公开(公告)号：US5838273A
公开(公告)日：1998-11-17
申请号：US907526
申请日：1997-08-08
申请人： Jens Sauerbrey , Oliver Kiehl
发明人： Jens Sauerbrey , Oliver Kiehl
CPC分类号： H03M1/0682 , H03M1/685 , H03M1/765
摘要： A fully differential resistor-string digital-to-analog converter wherein a resistor network having half the number of resistors of an otherwise standard digital-to-analog convertor of this type is enabled with the assistance of a first decoder, a second decoder and a subtraction unit thus reducing the required chip area and the overall switching time.
摘要翻译： 一种完全差分电阻串数模转换器，其中具有这种类型的其它标准数模转换器的电阻数量的一半的电阻器网络在第一解码器，第二解码器和 因此减少了所需的芯片面积和整个切换时间。
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公开(公告)号：US07203859B2
公开(公告)日：2007-04-10
申请号：US09932891
申请日：2001-08-20
申请人： Jens Sauerbrey , Martin Wittig , Roland Thewes
发明人： Jens Sauerbrey , Martin Wittig , Roland Thewes
IPC分类号： G06F1/04
CPC分类号： H03H19/00 , H03K5/1515 , H03K5/249
摘要： A clock configuration for driving switched op-amp circuits operated in opposite phases is presented in which a common off-phase of variable length is inserted between the on-phases of the individual operational amplifiers. The length of the off-phase can be adapted to the transient response of the operational amplifiers used. The clock configuration according to the invention can be used for further reducing the power consumption of switched op-amp circuits.
摘要翻译： 提出了用于驱动以相反相位操作的开关运算放大器电路的时钟配置，其中在各个运算放大器的同相之间插入可变长度的公共截止相位。 离相的长度可以适应所使用的运算放大器的瞬态响应。 根据本发明的时钟配置可用于进一步降低开关式运算放大器电路的功耗。
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3.发明申请Amplifier or filter circuit in switched capacitor circuit logic and method for amplifying or filtering signals 审中-公开开关电容电路中的放大器或滤波电路逻辑及放大或滤波信号的方法公开(公告)号：US20050116768A1
公开(公告)日：2005-06-02
申请号：US10181901
申请日：2001-01-08
申请人： Jens Sauerbrey
发明人： Jens Sauerbrey
CPC分类号： H03F3/45986 , H03F3/005 , H03F2200/331 , H03H19/004
摘要： An amplifier or filter circuit in switched capacitor circuit logic, comprising an amplifier or filter circuit in switched capacitor circuit logic with a switchable operation amplifier as an input stage of a switched opamp filter or amplifier circuit.
摘要翻译： 开关电容电路逻辑中的放大器或滤波器电路，包括开关电容器电路逻辑中的放大器或滤波器电路，其中可切换运算放大器作为开关运算放大器滤波器或放大器电路的输入级。
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公开(公告)号：US06559716B2
公开(公告)日：2003-05-06
申请号：US09932892
申请日：2001-08-20
申请人： Jens Sauerbrey , Martin Wittig
发明人： Jens Sauerbrey , Martin Wittig
IPC分类号： H03F102
CPC分类号： H03F3/72 , H03F3/45188 , H03F3/45192 , H03F2203/45396 , H03F2203/45506 , H03F2203/7203
摘要： A switchable operational amplifier is presented for switched op amp technology, in which the current through the pre-stage is reduced during the off phase of the switching clock pulse. In this way, power consumption can be reduced. During the off phase of the switching clock pulse, the current can either be reduced or switched off completely.
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5.发明授权Circuit configuration for forming a MOS capacitor with a lower voltage dependence and a lower area requirement 失效用于形成具有较低电压依赖性和较低面积要求的MOS电容器的电路配置公开(公告)号：US06700149B2
公开(公告)日：2004-03-02
申请号：US10113421
申请日：2002-04-01
IPC分类号： H01L27088
CPC分类号： H01L27/0805 , H01L29/94
摘要： A circuit configuration for providing a capacitance includes short-channel MOS transistors that are reverse-connected in series or in parallel, and that have the same channel type. When the short-channel MOS transistors are operated exclusively in the depletion mode in the required voltage range, the useful capacitance is increased, because of intrinsic capacitances, as compared with circuit configurations having conventional long-channel MOS transistors. These circuits greatly reduce the area taken up and reduce the costs.
摘要翻译： 用于提供电容的电路配置包括串联或并联反向并且具有相同通道类型的短沟道MOS晶体管。 当短沟道MOS晶体管仅在所需电压范围内的耗尽模式下工作时，与具有常规长沟道MOS晶体管的电路配置相比，由于固有电容，有用电容增加。 这些电路大大减少了占用的面积并降低了成本。
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公开(公告)号：US6067036A
公开(公告)日：2000-05-23
申请号：US71151
申请日：1998-05-04
申请人： Manfred Mauthe , Jens Sauerbrey
发明人： Manfred Mauthe , Jens Sauerbrey
CPC分类号： H03M7/3022
摘要： A digital-analog converter having high linearity is based on two sigma-delta modulators of second order which are fed back in a cascaded fashion and via differentiators. The first modulator has a quantizer with only three stages, an output signal of which delivers an analog output signal via a three-stage digital-analog converter and a low-pass filter. The particularly high linearity, the good stability and the relatively large bandwidth with reference to clock frequency are advantages of the digital-analog converter.
摘要翻译： 具有高线性度的数模转换器基于二级的两个Σ-Δ调制器，其以级联方式并通过微分器反馈。 第一调制器具有仅三级的量化器，其输出信号通过三级数模转换器和低通滤波器传送模拟输出信号。 参考时钟频率的特别高的线性度，良好的稳定性和相对较大的带宽是数模转换器的优点。
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