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16 条记录 (耗时 0.021 秒)

    Thin film multi-layered ceramic capacitor and method of manufacturing the same
    1.
    发明授权
    Thin film multi-layered ceramic capacitor and method of manufacturing the same 失效
    薄膜多层陶瓷电容器及其制造方法

    公开(公告)号：US06980413B1

    公开(公告)日：2005-12-27

    申请号：US11092544

    申请日：2005-03-29

    申请人： Jeong Wook Kim ,  Cheol Seong Hwang ,  Kang Heon Hur

    发明人： Jeong Wook Kim ,  Cheol Seong Hwang ,  Kang Heon Hur

    IPC分类号： H01G4/005 ,  H01G4/012 ,  H01G4/06 ,  H01G4/228 ,  H01G4/33 ,  H01G4/38

    CPC分类号： H01G4/33 ,  H01G4/012 ,  H01G4/38 ,  Y10T29/435

    摘要： The present invention provides a thin film type multi-layered ceramic capacitor including a stacked body composed of a plurality of capacitor layers. Each of the capacitor layers comprises a substrate having an upper surface where a plurality of holes are formed and a flat lower surface, and a thin film capacitor on the upper surface of the substrate. The thin film capacitor includes a lower electrode film, a dielectric film, and an upper electrode film. The lower electrode film, the dielectric film, and the upper electrode film are formed in sequence on the upper surface of the substrate. The lower and the upper electrode films extend to one side and the other side of the substrate and contact first and second external electrodes, respectively.

    摘要翻译： 本发明提供一种薄膜型多层陶瓷电容器，其包括由多个电容器层构成的层叠体。 每个电容器层包括具有形成多个孔的上表面和平坦的下表面的衬底，以及在衬底的上表面上的薄膜电容器。 薄膜电容器包括下电极膜，电介质膜和上电极膜。 下部电极膜，电介质膜和上部电极膜依次形成在基板的上表面上。 下电极膜和上电极膜分别延伸到衬底的一侧和另一侧，并分别接触第一和第二外部电极。

    Method and apparatus for interrupt handling in coarse grained array
    2.
    发明申请
    Method and apparatus for interrupt handling in coarse grained array 有权
    粗粒度阵列中断处理的方法和装置

    公开(公告)号：US20070162729A1

    公开(公告)日：2007-07-12

    申请号：US11519858

    申请日：2006-09-13

    申请人： Soo Jung Ryu ,  Jeong Wook Kim ,  Dong-Hoon Yoo ,  Hee Seok Kim

    发明人： Soo Jung Ryu ,  Jeong Wook Kim ,  Dong-Hoon Yoo ,  Hee Seok Kim

    IPC分类号： G06F9/44

    CPC分类号： G06F9/4812

    摘要： A processor including a coarse grained array including a plurality of function units and a plurality of register files, wherein a loop to be executed by the coarse grained array is split into a plurality of sub-loops, and when an interrupt request occurs while executing the sub-loop in the coarse grained array, the interrupt request is processed after the executing of the sub-loop is completed.

    摘要翻译： 一种包括包括多个功能单元和多个寄存器文件的粗粒度阵列的处理器，其中由粗粒度阵列执行的循环被分割成多个子循环，并且当执行中断请求时发生中断请求 在粗粒子数组中的子循环，中断请求在子循环执行完成后被处理。

    Method and apparatus for interrupt handling during loop processing in reconfigurable coarse grained array
    3.
    发明授权
    Method and apparatus for interrupt handling during loop processing in reconfigurable coarse grained array 有权
    在可重构粗粒度阵列中循环处理中的中断处理方法和装置

    公开(公告)号：US07529917B2

    公开(公告)日：2009-05-05

    申请号：US11519858

    申请日：2006-09-13

    申请人： Soo Jung Ryu ,  Jeong Wook Kim ,  Dong-Hoon Yoo ,  Hee Seok Kim

    发明人： Soo Jung Ryu ,  Jeong Wook Kim ,  Dong-Hoon Yoo ,  Hee Seok Kim

    IPC分类号： G06F9/00

    CPC分类号： G06F9/4812

    摘要： A processor including a coarse grained array including a plurality of function units and a plurality of register files, wherein a loop to be executed by the coarse grained array is split into a plurality of sub-loops, and when an interrupt request occurs while executing the sub-loop in the coarse grained array, the interrupt request is processed after the executing of the sub-loop is completed.

    摘要翻译： 一种包括包括多个功能单元和多个寄存器文件的粗粒度阵列的处理器，其中由粗粒度阵列执行的循环被分割成多个子循环，并且当执行中断请求时发生中断请求 在粗粒子数组中的子循环，中断请求在子循环执行完成后被处理。

    Method and system for early Z test in title-based three-dimensional rendering
    4.
    发明申请
    Method and system for early Z test in title-based three-dimensional rendering 审中-公开
    基于标题的三维渲染的早期Z检验方法与系统

    公开(公告)号：US20080068375A1

    公开(公告)日：2008-03-20

    申请号：US11655244

    申请日：2007-01-19

    申请人： Kyoung June Min ,  Jong Myon Kim ,  Hee Seok Kim ,  Jeong Wook Kim ,  Suk Jin Kim

    发明人： Kyoung June Min ,  Jong Myon Kim ,  Hee Seok Kim ,  Jeong Wook Kim ,  Suk Jin Kim

    IPC分类号： G06T15/40

    CPC分类号： G06T15/405

    摘要： A method and system for an early Z test in a tile-based three-dimensional rendering is provided. In the method and system for an early Z test, a portion which is not displayed to a user is removed prior to performing a rasterization process, and thereby performing the 3D rendering efficiently. The method includes segmenting a scene into tiles for performing a rendering with respect to a triangle; selecting a first tile of the tiles, which has a tile Z value less than a minimum Z value of the triangle; and performing the rendering with respect to the triangle in remaining tiles excluding the selected first tile of the tiles.

    摘要翻译： 提供了一种基于瓦片的三维渲染的早期Z检验的方法和系统。 在早期Z测试的方法和系统中，在执行光栅化处理之前去除了不向用户显示的部分，从而有效地执行3D渲染。 该方法包括将场景分割成用于执行相对于三角形的呈现的图块; 选择瓦片的第一瓦片，其具有小于所述三角形的最小Z值的瓦片Z值; 以及在除了所选择的瓦片的所选择的第一瓦片之外的剩余瓦片中执行相对于三角形的呈现。

    Apparatus and method of exception handling for reconfigurable architecture
    5.
    发明授权
    Apparatus and method of exception handling for reconfigurable architecture 有权
    可重构架构异常处理的装置和方法

    公开(公告)号：US09152418B2

    公开(公告)日：2015-10-06

    申请号：US11487407

    申请日：2006-07-17

    申请人： Hee Seok Kim ,  Dong-Hoon Yoo ,  Jeong Wook Kim ,  Soo Jung Ryu

    发明人： Hee Seok Kim ,  Dong-Hoon Yoo ,  Jeong Wook Kim ,  Soo Jung Ryu

    IPC分类号： G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/3012 ,  G06F9/30105 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3863

    摘要： A processor including a coarse grained array including a plurality of processing elements, a central register file including a first plurality of register files, a shadow central register file including a second plurality of register files, each of the second plurality of register files corresponding to each of the first plurality of register files included in the central register file, and a plurality of shadow register files, each of the plurality of shadow register files corresponding to each of a third plurality of register files included in predetermined processing elements selected from the plurality of processing elements.

    摘要翻译： 一种处理器，包括包括多个处理元件的粗粒子阵列，包括第一多个寄存器文件的中央寄存器文件，包括第二多个寄存器文件的影子中心寄存器文件，与每个寄存器文件相对应的第二多个寄存器堆中的每一个 包括在中央寄存器文件中的第一多个寄存器文件和多个影子寄存器文件，多个影子寄存器文件中的每一个对应于包括在从多个寄存器文件中选择的预定处理元件中的第三多个寄存器文件中的每一个 处理元件。

    Method and system for early Z test in title-based three-dimensional rendering
    6.
    发明授权
    Method and system for early Z test in title-based three-dimensional rendering 有权
    基于标题的三维渲染的早期Z检验方法与系统

    公开(公告)号：US08154547B2

    公开(公告)日：2012-04-10

    申请号：US13090924

    申请日：2011-04-20

    申请人： Kyoung June Min ,  Jong Myon Kim ,  Hee Seok Kim ,  Jeong Wook Kim ,  Suk Jin Kim

    发明人： Kyoung June Min ,  Jong Myon Kim ,  Hee Seok Kim ,  Jeong Wook Kim ,  Suk Jin Kim

    IPC分类号： G06T15/40

    CPC分类号： G06T15/405

    摘要： A method and system for an early Z test in a tile-based three-dimensional rendering is provided. In the method and system for an early Z test, a portion which is not displayed to a user is removed prior to performing a rasterization process, and thereby performing the 3D rendering efficiently. The method includes segmenting a scene into tiles for performing a rendering with respect to a triangle; selecting a first tile of the tiles, which has a tile Z value less than a minimum Z value of the triangle; and performing the rendering with respect to the triangle in remaining tiles excluding the selected first tile of the tiles.

    摘要翻译： 提供了一种基于瓦片的三维渲染的早期Z检验的方法和系统。 在早期Z测试的方法和系统中，在执行光栅化处理之前去除了不向用户显示的部分，从而有效地执行3D渲染。 该方法包括将场景分割成用于执行相对于三角形的呈现的图块; 选择瓦片的第一瓦片，其具有小于所述三角形的最小Z值的瓦片Z值; 以及在除了所选择的瓦片的所选择的第一瓦片之外的剩余瓦片中执行相对于三角形的呈现。

    Apparatus and method for optimizing loop buffer in reconfigurable processor
    8.
    发明申请
    Apparatus and method for optimizing loop buffer in reconfigurable processor 有权
    用于优化可重构处理器中循环缓冲器的装置和方法

    公开(公告)号：US20070150710A1

    公开(公告)日：2007-06-28

    申请号：US11525913

    申请日：2006-09-25

    申请人： Soo Jung Ryu ,  Jeong Wook Kim ,  Suk Jin Kim ,  Hong-Seok Kim

    发明人： Soo Jung Ryu ,  Jeong Wook Kim ,  Suk Jin Kim ,  Hong-Seok Kim

    IPC分类号： G06F9/44

    CPC分类号： G06F17/5054 ,  G06F9/381 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

    摘要： A reconfigurable processor comprising a configuration memory for storing a configuration bit for at least one loop configuration; a valid information memory for storing bit information indicating whether an operation in a loop is a delay operation; and at least one processing unit for determining whether an operation in a next cycle is the delay operation by referring to the bit information transmitted from the valid information memory, and selectively performing a change and an implementation of a configuration according to the configuration bit from the configuration memory based on the determined results.

    摘要翻译： 一种可重配置处理器，包括用于存储用于至少一个环路配置的配置位的配置存储器; 用于存储指示循环中的操作是否为延迟操作的位信息的有效信息存储器; 以及至少一个处理单元，用于通过参考从有效信息存储器发送的比特信息来确定下一个周期中的操作是否是延迟操作，并且根据来自所述有用信息存储器的配置位选择性地执行改变和配置的实现 基于确定结果的配置存储器。