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    Method and system for early Z test in title-based three-dimensional rendering
    3.
    发明申请
    Method and system for early Z test in title-based three-dimensional rendering 审中-公开
    基于标题的三维渲染的早期Z检验方法与系统

    公开(公告)号：US20080068375A1

    公开(公告)日：2008-03-20

    申请号：US11655244

    申请日：2007-01-19

    申请人： Kyoung June Min ,  Jong Myon Kim ,  Hee Seok Kim ,  Jeong Wook Kim ,  Suk Jin Kim

    发明人： Kyoung June Min ,  Jong Myon Kim ,  Hee Seok Kim ,  Jeong Wook Kim ,  Suk Jin Kim

    IPC分类号： G06T15/40

    CPC分类号： G06T15/405

    摘要： A method and system for an early Z test in a tile-based three-dimensional rendering is provided. In the method and system for an early Z test, a portion which is not displayed to a user is removed prior to performing a rasterization process, and thereby performing the 3D rendering efficiently. The method includes segmenting a scene into tiles for performing a rendering with respect to a triangle; selecting a first tile of the tiles, which has a tile Z value less than a minimum Z value of the triangle; and performing the rendering with respect to the triangle in remaining tiles excluding the selected first tile of the tiles.

    摘要翻译： 提供了一种基于瓦片的三维渲染的早期Z检验的方法和系统。 在早期Z测试的方法和系统中，在执行光栅化处理之前去除了不向用户显示的部分，从而有效地执行3D渲染。 该方法包括将场景分割成用于执行相对于三角形的呈现的图块; 选择瓦片的第一瓦片，其具有小于所述三角形的最小Z值的瓦片Z值; 以及在除了所选择的瓦片的所选择的第一瓦片之外的剩余瓦片中执行相对于三角形的呈现。

    METHOD AND SYSTEM FOR EARLY Z TEST IN TITLE-BASED THREE-DIMENSIONAL RENDERING
    4.
    发明申请
    METHOD AND SYSTEM FOR EARLY Z TEST IN TITLE-BASED THREE-DIMENSIONAL RENDERING 有权
    用于基于三维三维渲染的早期Z测试的方法和系统

    公开(公告)号：US20110193862A1

    公开(公告)日：2011-08-11

    申请号：US13090924

    申请日：2011-04-20

    申请人： Kyoung June MIN ,  Jong Myon Kim ,  Hee Seok Kim ,  Jeong Wook Kim ,  Suk Jin Kim

    发明人： Kyoung June MIN ,  Jong Myon Kim ,  Hee Seok Kim ,  Jeong Wook Kim ,  Suk Jin Kim

    IPC分类号： G06T15/00

    CPC分类号： G06T15/405

    摘要： A method and system for an early Z test in a tile-based three-dimensional rendering is provided. In the method and system for an early Z test, a portion which is not displayed to a user is removed prior to performing a rasterization process, and thereby performing the 3D rendering efficiently. The method includes segmenting a scene into tiles for performing a rendering with respect to a triangle; selecting a first tile of the tiles, which has a tile Z value less than a minimum Z value of the triangle; and performing the rendering with respect to the triangle in remaining tiles excluding the selected first tile of the tiles.

    摘要翻译： 提供了一种基于瓦片的三维渲染的早期Z检验的方法和系统。 在早期Z测试的方法和系统中，在执行光栅化处理之前去除了不向用户显示的部分，从而有效地执行3D渲染。 该方法包括将场景分割成用于执行相对于三角形的呈现的图块; 选择瓦片的第一瓦片，其具有小于所述三角形的最小Z值的瓦片Z值; 以及在除了所选择的瓦片的所选择的第一瓦片之外的剩余瓦片中执行相对于三角形的呈现。

    Method and system for early Z test in title-based three-dimensional rendering
    5.
    发明授权
    Method and system for early Z test in title-based three-dimensional rendering 有权
    基于标题的三维渲染的早期Z检验方法与系统

    公开(公告)号：US08154547B2

    公开(公告)日：2012-04-10

    申请号：US13090924

    申请日：2011-04-20

    申请人： Kyoung June Min ,  Jong Myon Kim ,  Hee Seok Kim ,  Jeong Wook Kim ,  Suk Jin Kim

    发明人： Kyoung June Min ,  Jong Myon Kim ,  Hee Seok Kim ,  Jeong Wook Kim ,  Suk Jin Kim

    IPC分类号： G06T15/40

    CPC分类号： G06T15/405

    摘要： A method and system for an early Z test in a tile-based three-dimensional rendering is provided. In the method and system for an early Z test, a portion which is not displayed to a user is removed prior to performing a rasterization process, and thereby performing the 3D rendering efficiently. The method includes segmenting a scene into tiles for performing a rendering with respect to a triangle; selecting a first tile of the tiles, which has a tile Z value less than a minimum Z value of the triangle; and performing the rendering with respect to the triangle in remaining tiles excluding the selected first tile of the tiles.

    摘要翻译： 提供了一种基于瓦片的三维渲染的早期Z检验的方法和系统。 在早期Z测试的方法和系统中，在执行光栅化处理之前去除了不向用户显示的部分，从而有效地执行3D渲染。 该方法包括将场景分割成用于执行相对于三角形的呈现的图块; 选择瓦片的第一瓦片，其具有小于所述三角形的最小Z值的瓦片Z值; 以及在除了所选择的瓦片的所选择的第一瓦片之外的剩余瓦片中执行相对于三角形的呈现。

    Apparatus and method for optimizing loop buffer in reconfigurable processor
    7.
    发明授权
    Apparatus and method for optimizing loop buffer in reconfigurable processor 有权
    用于优化可重构处理器中循环缓冲器的装置和方法

    公开(公告)号：US07478227B2

    公开(公告)日：2009-01-13

    申请号：US11525913

    申请日：2006-09-25

    申请人： Soo Jung Ryu ,  Jeong Wook Kim ,  Suk Jin Kim ,  Hong-Seok Kim

    发明人： Soo Jung Ryu ,  Jeong Wook Kim ,  Suk Jin Kim ,  Hong-Seok Kim

    IPC分类号： G06F9/40

    CPC分类号： G06F17/5054 ,  G06F9/381 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

    摘要： A reconfigurable processor comprising a configuration memory for storing a configuration bit for at least one loop configuration; a valid information memory for storing bit information indicating whether an operation in a loop is a delay operation; and at least one processing unit for determining whether an operation in a next cycle is the delay operation by referring to the bit information transmitted from the valid information memory, and selectively performing a change and an implementation of a configuration according to the configuration bit from the configuration memory based on the determined results.

    摘要翻译： 一种可重配置处理器，包括用于存储用于至少一个环路配置的配置位的配置存储器; 用于存储指示循环中的操作是否为延迟操作的位信息的有效信息存储器; 以及至少一个处理单元，用于通过参考从有效信息存储器发送的比特信息来确定下一个周期中的操作是否是延迟操作，并且根据来自所述有用信息存储器的配置位选择性地执行改变和配置的实现 基于确定结果的配置存储器。

    Processor and method of performing speculative load operations of the processor
    8.
    发明授权
    Processor and method of performing speculative load operations of the processor 有权
    处理器和执行处理器的推测加载操作的方法

    公开(公告)号：US08443174B2

    公开(公告)日：2013-05-14

    申请号：US11838488

    申请日：2007-08-14

    申请人： Hong-Seok Kim ,  Hee Seok Kim ,  Jeongwook Kim ,  Suk Jin Kim

    发明人： Hong-Seok Kim ,  Hee Seok Kim ,  Jeongwook Kim ,  Suk Jin Kim

    IPC分类号： G06F9/30 ,  G06F9/312

    CPC分类号： G06F9/3842

    摘要： Provided is a processor and method of performing speculative load instructions of the processor in which a load instruction is performed only in the case where the load instruction substantially accesses a memory. A load instruction for canceling operations is performed in other cases except the above case, so that problems occurring by accessing an input/output (I/O) mapped memory area and the like at the time of performing speculative load instructions can be prevented using only a software-like method, thereby improving the performance of a processor.

    摘要翻译： 提供了一种执行处理器的推测性加载指令的处理器和方法，其中仅在加载指令基本访问存储器的情况下执行加载指令。 在除了上述情况之外的其他情况下执行用于取消操作的加载指令，使得仅在执行推测性加载指令时访问输入/输出（I / O）映射存储区等而出现的问题可以仅被使用 一种类似软件的方法，从而提高处理器的性能。

    Apparatus and method for optimizing loop buffer in reconfigurable processor
    9.
    发明申请
    Apparatus and method for optimizing loop buffer in reconfigurable processor 有权
    用于优化可重构处理器中循环缓冲器的装置和方法

    公开(公告)号：US20070150710A1

    公开(公告)日：2007-06-28

    申请号：US11525913

    申请日：2006-09-25

    申请人： Soo Jung Ryu ,  Jeong Wook Kim ,  Suk Jin Kim ,  Hong-Seok Kim

    发明人： Soo Jung Ryu ,  Jeong Wook Kim ,  Suk Jin Kim ,  Hong-Seok Kim

    IPC分类号： G06F9/44

    CPC分类号： G06F17/5054 ,  G06F9/381 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

    摘要： A reconfigurable processor comprising a configuration memory for storing a configuration bit for at least one loop configuration; a valid information memory for storing bit information indicating whether an operation in a loop is a delay operation; and at least one processing unit for determining whether an operation in a next cycle is the delay operation by referring to the bit information transmitted from the valid information memory, and selectively performing a change and an implementation of a configuration according to the configuration bit from the configuration memory based on the determined results.

    摘要翻译： 一种可重配置处理器，包括用于存储用于至少一个环路配置的配置位的配置存储器; 用于存储指示循环中的操作是否为延迟操作的位信息的有效信息存储器; 以及至少一个处理单元，用于通过参考从有效信息存储器发送的比特信息来确定下一个周期中的操作是否是延迟操作，并且根据来自所述有用信息存储器的配置位选择性地执行改变和配置的实现 基于确定结果的配置存储器。

    PROCESSOR AND METHOD OF PERFORMING SPECULATIVE LOAD OPERATIONS OF THE PROCESSOR
    10.
    发明申请
    PROCESSOR AND METHOD OF PERFORMING SPECULATIVE LOAD OPERATIONS OF THE PROCESSOR 有权
    处理器的执行和执行分析负载运算的方法

    公开(公告)号：US20080209188A1

    公开(公告)日：2008-08-28

    申请号：US11838488

    申请日：2007-08-14

    申请人： Hong-Seok Kim ,  Hee Seok Kim ,  Jeongwook Kim ,  Suk Jin Kim

    发明人： Hong-Seok Kim ,  Hee Seok Kim ,  Jeongwook Kim ,  Suk Jin Kim

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3842

    摘要： Provided is a processor and method of performing speculative load instructions of the processor in which a load instruction is performed only in the case where the load instruction substantially accesses a memory. A load instruction for canceling operations is performed in other cases except the above case, so that problems occurring by accessing an input/output (I/O) mapped memory area and the like at the time of performing speculative load instructions can be prevented using only a software-like method, thereby improving the performance of a processor.

    摘要翻译： 提供了一种执行处理器的推测性加载指令的处理器和方法，其中仅在加载指令基本访问存储器的情况下执行加载指令。 在除了上述情况之外的其他情况下执行用于取消操作的加载指令，使得仅在执行推测性加载指令时访问输入/输出（I / O）映射存储区等而出现的问题可以仅被使用 一种类似软件的方法，从而提高处理器的性能。