公开(公告)号：US20050245029A1

公开(公告)日：2005-11-03

申请号：US11170467

申请日：2005-06-29

申请人： Jeong-hyuk Choi ,  Wang-chul Shin ,  Jin-hyun Shin

发明人： Jeong-hyuk Choi ,  Wang-chul Shin ,  Jin-hyun Shin

IPC分类号： H01L29/788 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/331

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating a flash memory device. Parallel mask patterns are formed on a substrate. The substrate is etched using the mask patterns to form trenches. An insulating layer pattern is formed in the trenches and an area between the mask patterns. The mask patterns are removed to expose an upper sidewall of the insulating layer pattern that protrudes away from a top surface of the substrate. The insulating layer pattern is isotropically etched to form sloped sidewalls that protrude away from the top surface of the substrate.

摘要翻译： 一种制造闪速存储器件的方法。 在基板上形成平行的掩膜图案。 使用掩模图案蚀刻衬底以形成沟槽。 在沟槽中形成绝缘层图案和掩模图案之间的区域。 去除掩模图案以暴露远离基板的顶表面突出的绝缘层图案的上侧壁。 绝缘层图案被各向同性地蚀刻以形成从衬底顶表面突出的倾斜侧壁。

公开(公告)号：US06927447B2

公开(公告)日：2005-08-09

申请号：US10447254

申请日：2003-05-28

申请人： Jeong-hyuk Choi ,  Wang-chul Shin ,  Jin-hyun Shin

发明人： Jeong-hyuk Choi ,  Wang-chul Shin ,  Jin-hyun Shin

IPC分类号： H01L29/788 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating a flash memory device. Parallel mask patterns are formed on a substrate. The substrate is etched using the mask patterns to form trenches. An insulating layer pattern is formed in the trenches and an area between the mask patterns. The mask patterns are removed to expose an upper sidewall of the insulating layer pattern that protrudes away from a top surface of the substrate. The insulating layer pattern is isotropically etched to form sloped sidewalls that protrude away from the top surface of the substrate.

摘要翻译： 一种制造闪速存储器件的方法。 在基板上形成平行的掩膜图案。 使用掩模图案蚀刻衬底以形成沟槽。 在沟槽中形成绝缘层图案和掩模图案之间的区域。 去除掩模图案以暴露远离基板的顶表面突出的绝缘层图案的上侧壁。 绝缘层图案被各向同性地蚀刻以形成从衬底顶表面突出的倾斜侧壁。

公开(公告)号：US07494868B2

公开(公告)日：2009-02-24

申请号：US11170467

申请日：2005-06-29

申请人： Jeong-hyuk Choi ,  Wang-chul Shin ,  Jin-hyun Shin

发明人： Jeong-hyuk Choi ,  Wang-chul Shin ,  Jin-hyun Shin

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating a flash memory device. Parallel mask patterns are formed on a substrate. The substrate is etched using the mask patterns to form trenches. An insulating layer pattern is formed in the trenches and an area between the mask patterns. The mask patterns are removed to expose an upper sidewall of the insulating layer pattern that protrudes away from a top surface of the substrate. The insulating layer pattern is isotropically etched to form sloped sidewalls that protrude away from the top surface of the substrate.

摘要翻译： 一种制造闪速存储器件的方法。 在基板上形成平行的掩膜图案。 使用掩模图案蚀刻衬底以形成沟槽。 在沟槽中形成绝缘层图案和掩模图案之间的区域。 去除掩模图案以暴露远离基板的顶表面突出的绝缘层图案的上侧壁。 绝缘层图案被各向同性地蚀刻以形成从衬底顶表面突出的倾斜侧壁。

公开(公告)号：US6028788A

公开(公告)日：2000-02-22

申请号：US922047

申请日：1997-09-02

申请人： Jeong-hyuk Choi ,  Wang-chul Shin

发明人： Jeong-hyuk Choi ,  Wang-chul Shin

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/10

摘要： A flash memory device for providing high integration and high-speed data access has string blocks arranged in a two-dimensional manner. Each string block has a plurality of strings, at least one bit line select line, a plurality of word lines, a plurality of source line select lines, a first dual-mode line, and a second dual-mode line. Each string is constructed such that at least one bit line select transistor, a plurality of unit memory cells, and a plurality of source line select transistors are connected in series. The bit line select lines are connected to respective gates of the bit line select transistors. The plurality of word lines are connected to respective control gates of the plurality of unit memory cells. The first dual-mode line is connected to one end of each of the strings in a first string block through a bit line contact, and the second dual-mode line is connected to other end of each of the strings in the first string block through a source line contact. Additionally, the first dual-mode line is connected to the source line contact of a second string block while the second dual-mode line is connected to the bit line contact of a third string block.

摘要翻译： 用于提供高集成度和高​​速数据访问的快闪存储器件具有以二维方式布置的串块。 每个串块具有多个串，至少一个位线选择线，多个字线，多个源极线选择线，第一双模式线和第二双模式线。 每个串构造成使得至少一个位线选择晶体管，多个单元存储单元和多个源极线选择晶体管串联连接。 位线选择线连接到位线选择晶体管的各个栅极。 多个字线连接到多个单元存储单元的相应控制栅极。 第一双模式线通过位线接触连接到第一串块中的每个串的一端，并且第二双模线连接到第一串块中的每个串的另一端 源线接触。 此外，第一双模式线连接到第二串块的源极线接触，而第二双模线连接到第三串块的位线接触。

公开(公告)号：US06204122B1

公开(公告)日：2001-03-20

申请号：US08932641

申请日：1997-09-17

申请人： Kyung-joong Joo ,  Jeong-hyuk Choi ,  Wang-chul Shin

发明人： Kyung-joong Joo ,  Jeong-hyuk Choi ,  Wang-chul Shin

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42324

摘要： Methods of forming nonvolatile integrated circuit memory devices having high capacitive coupling ratios include the steps of forming a tunneling oxide layer on a face of a semiconductor substrate and then forming a forming a first conductive layer (e.g., doped polysilicon) on the tunneling oxide layer. A floating gate electrode mask is then patterned on the first conductive layer so as to expose a portion the first conductive layer. A second conductive layer is then patterned on the exposed portion of the first conductive layer and on sidewalls of the floating gate electrode mask, to define a concave or U-shaped floating gate electrode having conductive sidewall extensions. The sidewall extensions increase the effective area of the floating gate electrode and increase the capacitance coupling ratio which enables programming and erasing at reduced voltage levels. A first electrically insulating layer is then formed on the U-shaped floating gate electrode, opposite the tunneling oxide layer. A control gate is then formed on the first electrically insulating layer, opposite the U-shaped floating gate electrode.

摘要翻译： 形成具有高电容耦合比的非易失性集成电路存储器件的方法包括以下步骤：在半导体衬底的表面上形成隧穿氧化物层，然后在隧道氧化物层上形成第一导电层（例如掺杂多晶硅）。 然后在第一导电层上图案化浮栅电极掩模，以暴露第一导电层的一部分。 然后在第一导电层的暴露部分和浮栅电极掩模的侧壁上将第二导电层图案化，以限定具有导电侧壁延伸部的凹形或U形浮栅。 侧壁延伸增加了浮栅电极的有效面积并增加了电容耦合比，这使得能够在降低的电压电平下进行编程和擦除。 然后在U形浮栅上形成第一电绝缘层，与隧道氧化物层相对。 然后在与U形浮栅相对的第一电绝缘层上形成控制栅。

公开(公告)号：US06180457B2

公开(公告)日：2001-01-30

申请号：US09405534

申请日：1999-09-24

申请人： Wang-chul Shin ,  Jeong-eui Kang ,  Kyong-moo Mang

发明人： Wang-chul Shin ,  Jeong-eui Kang ,  Kyong-moo Mang

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/11536

摘要： A method of manufacturing a non-volatile memory device is provided. According to an aspect of this method, an isolation layer is formed on a semiconductor substrate including a cell array part and a peripheral circuit part. A floating gate pattern is formed exposing the semiconductor substrate in the peripheral circuit part with a tunnel oxide layer interposed between the floating gate pattern and the semiconductor substrate in the cell array part, and an interlayer insulating layer covering the floating gate pattern is formed. A control gate layer is formed, which covers the interlayer insulating layer and the semiconductor substrate in the peripheral circuit part while interposing a gate oxide layer between the control gate layer and the semiconductor substrate. The isolation layer in the peripheral circuit part is protected by leaving a part of the control gate layer covering the peripheral circuit part, and a control gate, an interlayer insulating layer pattern, and a floating gate in the cell array part are formed by sequentially patterning the control gate layer, the interlayer insulating layer, and the floating gate pattern in the cell array part. A first low-concentration impurity layer is formed by first ion-implantation of arsenic into the semiconductor substrate adjacent to the floating gate using the control gate and the control gate layer covering the peripheral circuit part as an ion-implantation mask. A gate is formed in the peripheral circuit part by patterning the control gate layer in the peripheral circuit part with a photo resist pattern shielding the cell array part. A second low-concentration impurity layer is formed by second ion-implantation of second impurities, phosphorous, into the semiconductor substrate adjacent to the gate using the photo resist pattern as an ion-implantation mask.

摘要翻译： 提供一种制造非易失性存储器件的方法。 根据该方法的一个方面，在包括电池阵列部分和外围电路部分的半导体衬底上形成隔离层。 形成在栅极阵列部分中插入在浮置栅极图案和半导体衬底之间的隧道氧化层的外围电路部分中的半导体衬底暴露的浮栅图案，并且形成覆盖浮栅图案的层间绝缘层。 形成控制栅极层，其在外围电路部分中覆盖层间绝缘层和半导体衬底，同时在控制栅极层和半导体衬底之间插入栅极氧化物层。 通过使覆盖外围电路部分的控制栅极层的一部分留下外围电路部分中的隔离层，并且通过顺序地图案化形成电池阵列部分中的控制栅极，层间绝缘层图案和浮置栅极 控制栅极层，层间绝缘层和电池阵列部分中的浮动栅极图案。 通过使用控制栅极和覆盖外围电路部分的控制栅极层作为离子注入掩模，首先将砷离子注入到与浮置栅极相邻的半导体衬底中，形成第一低浓度杂质层。 通过利用屏蔽单元阵列部分的光致抗蚀剂图案对外围电路部分中的控制栅极层进行图案化，在外围电路部分中形成栅极。 通过使用光致抗蚀剂图案作为离子注入掩模，将第二杂质（磷）第二离子注入与栅极相邻的半导体衬底中来形成第二低浓度杂质层。