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12 条记录 (耗时 0.018 秒)

    Five port module as a node in an asynchronous speed independent network of concurrent processors
    1.
    发明授权
    Five port module as a node in an asynchronous speed independent network of concurrent processors 失效
    五端口模块作为节点在异步速度独立的并发处理器网络中

    公开(公告)号：US4482996A

    公开(公告)日：1984-11-13

    申请号：US414071

    申请日：1982-09-02

    申请人： Jesse R. Wilson ,  Gary L. Logsdon

    发明人： Jesse R. Wilson ,  Gary L. Logsdon

    IPC分类号： G06F15/177 ,  G06F15/173 ,  G06F15/80 ,  H04J6/00

    CPC分类号： G06F15/17375 ,  G06F15/80

    摘要： A five port module as a node in an asynchronous speed independent network of concurrent processors, each port of the module including an input selector switch and an output selector switch such that each selector switch has a plurality of output channels one for each of the output arbiter switches (except the arbiter switch associated with its own port). Each selector switch is adapted to select a particular output channel (arbiter switch) according to the initial bits received in the asynchronous speed independent message. In this manner, the module of the present invention can accommodate up to five simultaneous asynchronous message transmissions without nodal blocking although the average number of simultaneous messages that can be accommodated will be less. The respective arbiter and selector switches are provided with circuitry to respond to a clear signal that resets the corresponding arbiter and selector switches forming a particular transmission path should nodal blocking occur.

    摘要翻译： 作为并行处理器的异步速度独立网络中的节点的五端口模块，模块的每个端口包括输入选择器开关和输出选择器开关，使得每个选择器开关具有多个输出通道，用于每个输出仲裁器 交换机（与其自己的端口相关联的仲裁器交换机除外）。 每个选择器开关适于根据在异步速度独立消息中接收到的初始位选择特定的输出通道（仲裁器开关）。 以这种方式，本发明的模块可以容纳多达五个不同节点的同步异步消息传输，尽管可以容纳的同时消息的平均数量将较少。 相应的仲裁器和选择器开关设置有电路，用于响应清除信号，该清除信号复位相应的仲裁器和选择器开关，形成特定传输路径，如果发生节点阻塞。

    Four way arbiter switch for a five port module as a node in an asynchronous speed independent network of concurrent processors
    2.
    发明授权
    Four way arbiter switch for a five port module as a node in an asynchronous speed independent network of concurrent processors 失效
    四路仲裁器交换机，用于将五端口模块作为异步速度独立并发处理器网络中的一个节点

    公开(公告)号：US4475188A

    公开(公告)日：1984-10-02

    申请号：US414069

    申请日：1982-09-02

    申请人： Jesse R. Wilson ,  Gary L. Logsdon

    发明人： Jesse R. Wilson ,  Gary L. Logsdon

    IPC分类号： G06F15/16 ,  G06F15/173 ,  G06F15/80 ,  H04J6/00

    CPC分类号： G06F15/17375 ,  G06F15/80

    摘要： A four way arbiter switch for a five port module as a node in an asynchronous speed independent network of concurrent processors, each port of the module including an input selector switch and an output selector switch such that each selector switch has a plurality of output channels one for each of the output arbiter switches (except the arbiter switch associated with its own port). Each selector switch is adapted to select a particular output channel (arbiter switch) according to the initial bits received in the asynchronous speed independent message. In this manner, the module of the present invention can accommodate up to five simultaneous asynchronous message transmissions without nodal blocking although the average number of simultaneous messages that can be accommodated will be less. The respective arbiter and selector switches are provided with circuitry to respond to a clear signal that resets the corresponding arbiter and selector switches forming a particular transmission path should nodal blocking occur.

    摘要翻译： 一种用于五端口模块作为并行处理器的异步速度独立网络中的节点的四路仲裁器交换机，模块的每个端口包括输入选择器开关和输出选择器开关，使得每个选择器开关具有多个输出通道 对于每个输出仲裁器开关（除了与其自己的端口相关联的仲裁器开关外）。 每个选择器开关适于根据在异步速度独立消息中接收到的初始位选择特定的输出通道（仲裁器开关）。 以这种方式，本发明的模块可以容纳多达五个不同节点的同步异步消息传输，尽管可以容纳的同时消息的平均数量将较少。 相应的仲裁器和选择器开关设置有电路，用于响应清除信号，该清除信号复位相应的仲裁器和选择器开关，形成特定传输路径，如果发生节点阻塞。

    Four way selector switch for a five port module as a node asynchronous speed independent network of concurrent processors
    5.
    发明授权
    Four way selector switch for a five port module as a node asynchronous speed independent network of concurrent processors 失效
    四路选择开关为五端口模块作为节点异步速度独立的并发处理器网络

    公开(公告)号：US4484325A

    公开(公告)日：1984-11-20

    申请号：US414070

    申请日：1982-09-02

    申请人： Jesse R. Wilson ,  Gary L. Logsdon

    发明人： Jesse R. Wilson ,  Gary L. Logsdon

    IPC分类号： G06F15/16 ,  G06F13/14 ,  G06F13/40 ,  G06F15/173 ,  G06F15/80 ,  H04J6/00

    CPC分类号： G06F13/4022 ,  G06F13/14 ,  G06F15/80

    摘要： A four way selector switch for a five port module as a node in an asynchronous speed independent network of concurrent processors, each port of the module including an input selector switch and an output selector switch such that each selector switch has a plurality of output channels one for each of the output arbiter switches (except the arbiter switch associated with its own port). Each selector switch is adapted to select a particular output channel (arbiter switch) according to the initial bits received in the asynchronous speed independent message. In this manner, the module of the present invention can accommodate up to five simultaneous asynchronous message transmissions without nodal blocking although the average number of simultaneous messages that can be accommodated will be less. The respective arbiter and selector switches are provided with circuitry to respond to a clear signal that resets the corresponding arbiter and selector switches forming a particular transmission path should nodal blocking occur.

    摘要翻译： 一种用于五端口模块作为并行处理器的异步速度独立网络中的节点的四路选择器开关，模块的每个端口包括输入选择器开关和输出选择器开关，使得每个选择器开关具有多个输出通道 对于每个输出仲裁器开关（除了与其自己的端口相关联的仲裁器开关外）。 每个选择器开关适于根据在异步速度独立消息中接收到的初始位选择特定的输出通道（仲裁器开关）。 以这种方式，本发明的模块可以容纳多达五个不同节点的同步异步消息传输，尽管可以容纳的同时消息的平均数量将较少。 相应的仲裁器和选择器开关设置有电路，用于响应清除信号，该清除信号复位相应的仲裁器和选择器开关，形成特定传输路径，如果发生节点阻塞。

    System memory for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes
    6.
    发明授权
    System memory for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes 失效
    用于还原处理器的系统存储器评估使用无变量应用语言代码存储为二进制定向图的程序

    公开(公告)号：US4616315A

    公开(公告)日：1986-10-07

    申请号：US690842

    申请日：1985-01-11

    申请人： Gary L. Logsdon ,  Mark R. Scheevel ,  Michael A. Winchell

    发明人： Gary L. Logsdon ,  Mark R. Scheevel ,  Michael A. Winchell

    IPC分类号： G06F12/00 ,  G06F9/44 ,  G06F9/45

    CPC分类号： G06F9/4436

    摘要： A system memory for a reduction processor which evaluates programs stored as binary graphs employing variable-free applicative language codes. These graphs are made up of nodes, each of which exists in memory and contains as its most significant bit a mark bit which when set indicates that the node is being used in a graph and when reset indicates that the node or storage location is available for future use by the processor. In order to accommodate the scanning of a number of storage locations in parallel, the system memory is divided into a node memory and the mark bit memory so that the mark bits for a number of sequential storage locations can be examined in parallel to determine which node locations are free for use by the graph manager.

    摘要翻译： 一种用于还原处理器的系统存储器，其使用无变量的应用语言代码评估存储为二进制图形的程序。 这些图形由节点组成，每个节点都存在于存储器中，并且包含最高有效位的标记位，当设置指示节点正在图形中使用时，并且当复位指示节点或存储位置可用于 未来由处理器使用。 为了平行地适应多个存储位置的扫描，系统存储器被划分为节点存储器和标记位存储器，以便可并行地检查多个顺序存储位置的标记位以确定哪个节点 位置可由图表管理员自由使用。

    Allocator for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes
    8.
    发明授权
    Allocator for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes 失效
    用于还原处理器的分配器评估使用无变量应用语言代码存储为二进制定向图的程序

    公开(公告)号：US4598361A

    公开(公告)日：1986-07-01

    申请号：US690846

    申请日：1985-01-11

    申请人： Gary L. Logsdon ,  Mark R. Scheevel ,  Frank A. Williams, Jr.

    发明人： Gary L. Logsdon ,  Mark R. Scheevel ,  Frank A. Williams, Jr.

    IPC分类号： G06F12/00 ,  G06F9/44 ,  G06F12/02 ,  G06F1/00

    CPC分类号： G06F9/4436

    摘要： An allocator for a reduction processor which evaluates programs stored as binary graphs employing variable-free applicative language codes. These graphs are made up of nodes, each of which exists in memory and contains as its most significant bit a mark bit which when set indicates that the node is being used in a graph and when reset indicates that the node or storage location is available for future use by the processor. The allocator scans selected groups of storage locations in parallel to see if there are any unused storage locations and then places the addresses of those unused storage locations in a queue for use by the processor.

    摘要翻译： 用于还原处理器的分配器，其使用无变量的应用语言代码评估存储为二进制图的程序。 这些图形由节点组成，每个节点都存在于存储器中，并且包含最高有效位的标记位，当设置指示节点正在图形中使用时，并且当复位指示节点或存储位置可用于 未来由处理器使用。 分配器并行扫描所选择的存储位置组，以查看是否存在任何未使用的存储位置，然后将这些未使用的存储位置的地址放置在队列中以供处理器使用。