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1.发明申请SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS INTO A SINGLE DESTINATION USING A WRITEMASK 审中-公开使用WRITEMASK将两个源操作混合到单个目的地的系统，设备和方法公开(公告)号：US20120254588A1
公开(公告)日：2012-10-04
申请号：US13078864
申请日：2011-04-01
申请人： Jesus Corbal San Adrian , Bret L. Toll , Robert C. Valentine , Jeffrey G. Wiedemeier , Sridhar Samudrala , Milind Baburao Girkar , Andrew Thomas Forsyth , Elmoustapha Ould-Ahmed-Vall , Dennis R. Bradford , Lisa K. Wu
发明人： Jesus Corbal San Adrian , Bret L. Toll , Robert C. Valentine , Jeffrey G. Wiedemeier , Sridhar Samudrala , Milind Baburao Girkar , Andrew Thomas Forsyth , Elmoustapha Ould-Ahmed-Vall , Dennis R. Bradford , Lisa K. Wu
IPC分类号： G06F9/30
CPC分类号： G06F9/30192 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30043
摘要： Embodiments of systems, apparatuses, and methods for performing a blend instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a data element-by-element selection of data elements of first and second source operands using the corresponding bit positions of a writemask as a selector between the first and second operands and storage of the selected data elements into the destination at the corresponding position in the destination.
摘要翻译： 描述了用于在计算机处理器中执行混合指令的系统，装置和方法的实施例。 在一些实施例中，混合指令的执行使用作为第一操作数和第二操作数之间的选择器的写入掩码的相应比特位置，逐个元素地选择第一和第二源操作数的数据元素，并存储所选择的 数据元素到达目的地的目标位置。
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公开(公告)号：US20120254589A1
公开(公告)日：2012-10-04
申请号：US13078868
申请日：2011-04-01
申请人： Jesus Corbal San Adrian , Roger Espasa Sans , Milind Baburao Girkar , Lisa K. Wu , Dennis R. Bradford , Victor W. Lee
发明人： Jesus Corbal San Adrian , Roger Espasa Sans , Milind Baburao Girkar , Lisa K. Wu , Dennis R. Bradford , Victor W. Lee
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30032 , G06F9/30192
摘要： Embodiments of systems, apparatuses, and methods for performing an align instruction in a computer processor are described. In some embodiments, the execution of an align instruction causes the selective storage of data elements of two concatenated sources to be stored in a destination.
摘要翻译： 描述了用于在计算机处理器中执行对准指令的系统，装置和方法的实施例。 在一些实施例中，对齐指令的执行导致将两个级联源的数据元素的选择性存储存储在目的地中。
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公开(公告)号：US20140095831A1
公开(公告)日：2014-04-03
申请号：US13631071
申请日：2012-09-28
申请人： Edward T. Grochowski , Dennis R. Bradford , George Z. Chrysos , Andrew T. Forsyth , Michael D. Upton , Lisa K. Wu
发明人： Edward T. Grochowski , Dennis R. Bradford , George Z. Chrysos , Andrew T. Forsyth , Michael D. Upton , Lisa K. Wu
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30043 , G06F9/30145 , G06F9/345 , G06F9/355
摘要： An apparatus and method are described for performing efficient gather operations in a pipelined processor. For example, a processor according to one embodiment of the invention comprises: gather setup logic to execute one or more gather setup operations in anticipation of one or more gather operations, the gather setup operations to determine one or more addresses of vector data elements to be gathered by the gather operations; and gather logic to execute the one or more gather operations to gather the vector data elements using the one or more addresses determined by the gather setup operations.
摘要翻译： 描述了一种用于在流水线处理器中执行有效收集操作的装置和方法。 例如，根据本发明的一个实施例的处理器包括：收集设置逻辑，用于在预期一个或多个收集操作中执行一个或多个收集设置操作，所述收集设置操作确定向量数据元素的一个或多个地址 聚集在一起聚集; 并收集逻辑以执行一个或多个收集操作以使用由收集设置操作确定的一个或多个地址来收集向量数据元素。
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公开(公告)号：US20140164705A1
公开(公告)日：2014-06-12
申请号：US13976429
申请日：2011-12-22
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F9/30047 , G06F12/0811 , G06F12/0862
摘要： A method performed by a processor is described. The method includes executing an instruction. The instruction has an address as an operand. The executing of the instruction includes sending a signal to cache coherence protocol logic of the processor. In response to the signal, the cache coherence protocol logic issues a request for ownership of a cache line at the address. The cache line is not in a cache of the processor. The request for ownership also indicates that the cache line is not to be sent to the processor.
摘要翻译： 描述由处理器执行的方法。 该方法包括执行指令。 该指令具有作为操作数的地址。 指令的执行包括向处理器的高速缓存一致性协议逻辑发送信号。 响应于该信号，高速缓存一致性协议逻辑在地址处发出对高速缓存行的所有权的请求。 高速缓存行不在处理器的高速缓存中。 所有权请求也表示高速缓存行不被发送到处理器。
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公开(公告)号：US09766886B2
公开(公告)日：2017-09-19
申请号：US13977736
申请日：2011-12-16
IPC分类号： G06F9/302 , G06F9/315 , G06F17/17 , G09G5/00 , G06F15/76 , G06F9/30 , G06F9/38 , G06T3/40 , G06F15/80
CPC分类号： G06F9/30036 , G06F9/30007 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30109 , G06F9/30145 , G06F9/3016 , G06F9/30185 , G06F9/3836 , G06F15/8053 , G06F17/17 , G06T3/4007
摘要： Instructions and logic provide vector linear interpolation functionality. In some embodiments, responsive to an instruction specifying: a first operand from a set of vector registers, a size of each of the vector elements, a portion of the vector elements upon which to compute linear interpolations, a second operand from a set of vector registers, and a third operand; an execution unit, reads a first, a second and a third value of the size of vector elements from corresponding data fields in the first, the second and the third operand respectively and computes an interpolated value as the first value multiplied by the second value minus the second value multiplied by the third value plus the third value.
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公开(公告)号：US09792115B2
公开(公告)日：2017-10-17
申请号：US13976997
申请日：2011-12-23
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/3893
摘要： A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c.
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公开(公告)号：US09430389B2
公开(公告)日：2016-08-30
申请号：US13976429
申请日：2011-12-22
CPC分类号： G06F12/0815 , G06F9/30047 , G06F12/0811 , G06F12/0862
摘要： A method performed by a processor is described. The method includes executing an instruction. The instruction has an address as an operand. The executing of the instruction includes sending a signal to cache coherence protocol logic of the processor. In response to the signal, the cache coherence protocol logic issues a request for ownership of a cache line at the address. The cache line is not in a cache of the processor. The request for ownership also indicates that the cache line is not to be sent to the processor.
摘要翻译： 描述由处理器执行的方法。 该方法包括执行指令。 该指令具有作为操作数的地址。 指令的执行包括向处理器的高速缓存一致性协议逻辑发送信号。 响应于该信号，高速缓存一致性协议逻辑在地址处发出对高速缓存行的所有权的请求。 高速缓存行不在处理器的高速缓存中。 所有权请求也表示高速缓存行不被发送到处理器。
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公开(公告)号：US20140052969A1
公开(公告)日：2014-02-20
申请号：US13976997
申请日：2011-12-23
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/3893
摘要： A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c.
摘要翻译： 描述处理核心，其具有执行单元逻辑电路，其具有第一寄存器以存储第一向量输入操作数，第二寄存器存储第二向量输入操作数和第三寄存器以存储包含标量输入操作数a，b的打包数据结构 ， C。 执行单元逻辑电路还包括执行操作的乘法器（a *（第一向量输入操作数））+（b *（第二向量操作数））+ c。
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