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公开(公告)号：US09430389B2
公开(公告)日：2016-08-30
申请号：US13976429
申请日：2011-12-22
CPC分类号： G06F12/0815 , G06F9/30047 , G06F12/0811 , G06F12/0862
摘要： A method performed by a processor is described. The method includes executing an instruction. The instruction has an address as an operand. The executing of the instruction includes sending a signal to cache coherence protocol logic of the processor. In response to the signal, the cache coherence protocol logic issues a request for ownership of a cache line at the address. The cache line is not in a cache of the processor. The request for ownership also indicates that the cache line is not to be sent to the processor.
摘要翻译： 描述由处理器执行的方法。 该方法包括执行指令。 该指令具有作为操作数的地址。 指令的执行包括向处理器的高速缓存一致性协议逻辑发送信号。 响应于该信号，高速缓存一致性协议逻辑在地址处发出对高速缓存行的所有权的请求。 高速缓存行不在处理器的高速缓存中。 所有权请求也表示高速缓存行不被发送到处理器。
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公开(公告)号：US20140164705A1
公开(公告)日：2014-06-12
申请号：US13976429
申请日：2011-12-22
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F9/30047 , G06F12/0811 , G06F12/0862
摘要： A method performed by a processor is described. The method includes executing an instruction. The instruction has an address as an operand. The executing of the instruction includes sending a signal to cache coherence protocol logic of the processor. In response to the signal, the cache coherence protocol logic issues a request for ownership of a cache line at the address. The cache line is not in a cache of the processor. The request for ownership also indicates that the cache line is not to be sent to the processor.
摘要翻译： 描述由处理器执行的方法。 该方法包括执行指令。 该指令具有作为操作数的地址。 指令的执行包括向处理器的高速缓存一致性协议逻辑发送信号。 响应于该信号，高速缓存一致性协议逻辑在地址处发出对高速缓存行的所有权的请求。 高速缓存行不在处理器的高速缓存中。 所有权请求也表示高速缓存行不被发送到处理器。
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公开(公告)号：US20140149651A1
公开(公告)日：2014-05-29
申请号：US13685991
申请日：2012-11-27
申请人： Andrew T. Forsyth , Ramacharan Sundararaman , Eric Sprangle , John C. Mejia , Douglas M. Carmean , Mark C. Davis , Edward T. Grochowski , Robert D. Cavin
发明人： Andrew T. Forsyth , Ramacharan Sundararaman , Eric Sprangle , John C. Mejia , Douglas M. Carmean , Mark C. Davis , Edward T. Grochowski , Robert D. Cavin
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/123 , Y02D10/13
摘要： In an embodiment, a processor includes a decode logic to receive and decode a first memory access instruction to store data in a cache memory with a replacement state indicator of a first level, and to send the decoded first memory access instruction to a control logic. In turn, the control logic is to store the data in a first way of a first set of the cache memory and to store the replacement state indicator of the first level in a metadata field of the first way responsive to the decoded first memory access instruction. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括解码逻辑，用于接收和解码第一存储器访问指令以将数据存储在具有第一级的替换状态指示符的高速缓冲存储器中，并将解码的第一存储器访问指令发送到控制逻辑。 反过来，控制逻辑是以第一组高速缓冲存储器的第一种方式存储数据，并且响应于解码的第一存储器访问指令将第一级的替换状态指示符存储在第一方式的元数据字段中 。 描述和要求保护其他实施例。
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4.发明申请ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER IDENTIFIER (APIC ID) ASSIGNMENT FOR A MULTI-CORE PROCESSING UNIT 有权高级可编程中断控制器标识符（APIC ID）多核处理单元的分配公开(公告)号：US20140156896A1
公开(公告)日：2014-06-05
申请号：US13994104
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
发明人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign each active and eligible core a unique advanced programmable interrupt controller (APIC) identifier (ID). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned an APIC ID or as ineligible to be assigned the APIC ID.
摘要翻译： 在重新启动或重启包含多核处理器的系统之后，多核处理器可以为每个活动和合格的核心分配唯一的高级可编程中断控制器（APIC）标识符（ID）。 初始化逻辑可以将多个处理核心中的每一个的状态检测为活动或不活动。 初始化逻辑可以检测多个处理核心中的每个处理核心的属性符合分配APIC ID的资格，或者不符合APIC ID分配的资格。
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公开(公告)号：US09208124B2
公开(公告)日：2015-12-08
申请号：US13993663
申请日：2011-12-29
CPC分类号： G06F15/80 , G06F1/24 , G06F11/0709 , G06F11/0724 , G06F11/0757 , G06F13/14
摘要： This disclosure is directed to performing a controlled reset of one or more cores while maintaining operation of at least one other core in a multi-core processor. An initialization core may include reset logic that may detect a problematic core or core that is unresponsive or otherwise not operating properly. The initialization core may generate a packet that enables communication with the problematic core. The initialization core may send a reset packet to the problematic core to instruct the problematic core to perform a reset.
摘要翻译： 本公开涉及在多核处理器中保持至少一个其他核的操作的同时执行一个或多个核的受控复位。 初始化核心可以包括可以检测无响应的核心或核心的复位逻辑，或者否则其不能正常操作。 初始化核心可以生成能够与有问题的核心进行通信的分组。 初始化核心可以向有问题的核心发送重置分组，以指示有问题的核心执行复位。
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公开(公告)号：US09389657B2
公开(公告)日：2016-07-12
申请号：US13993614
申请日：2011-12-29
CPC分类号： G06F1/24 , G06F1/3228 , G06F9/4405 , G06F13/14
摘要： An initialization core may include reset logic that may detect a global reset signal (GRS). The initialization core may generate one or more packets that enable communication with the cores. The initialization core may send reset packets to each of the cores that instruct the cores to perform a reset. In some embodiments, the reset command may power-off the cores. The initialization core may then transmit unreset packets to each of the cores that instruct the cores to perform an unreset and power-on the cores. In some embodiments, the cores may resume operation automatically without receipt of the unreset packet. The transmission of the packets may be staggered (staged) to control the power-on of the processor and enable the processor unit to more slowly increase its power state.
摘要翻译： 初始化核心可以包括可以检测全局复位信号（GRS）的复位逻辑。 初始化核心可以生成一个或多个能够与核心通信的分组。 初始化内核可以向指定内核执行复位的每个内核发送复位数据包。 在一些实施例中，复位命令可以关闭核心。 然后，初始化内核可以将未重新分配的数据包发送到指示内核执行未分配和上电的核心的每个核心。 在一些实施例中，核可以自动地恢复运行而不接收未重新分组。 分组的传输可以是交错的（分段）以控制处理器的上电，并且使处理器单元能够更慢地增加其功率状态。
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7.发明申请METHOD AND APPARATUS TO SHARE MODIFIED DATA WITHOUT WRITE-BACK IN A SHARED-MEMORY MANY-CORE SYSTEM 审中-公开分享修改数据的方法和设备，无需在共享存储器多核系统中进行回写公开(公告)号：US20140189255A1
公开(公告)日：2014-07-03
申请号：US13731584
申请日：2012-12-31
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0822
摘要： A cache-coherent device may include multiple caches and a cache coherency engine, which monitors whether there are more than one versions of a cache line stored in the caches and whether the version of the cache line in the caches is consistent with the version of the cache line stored in the memory.
摘要翻译： 高速缓存一致设备可以包括多个高速缓存和高速缓存一致性引擎，该引擎监视高速缓存中存储的高速缓存行是否存在多于一个版本，高速缓存中的高速缓存行的版本是否与 缓存行存储在内存中。
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8.发明授权公开(公告)号：US08533436B2
公开(公告)日：2013-09-10
申请号：US12492652
申请日：2009-06-26
申请人： Joshua B. Fryman , Edward T. Grochowski , Toni Juan , Andrew Thomas Forsyth , John Mejia , Ramacharan Sundararaman , Eric Sprangle , Roger Espasa , Ravi Rajwar
发明人： Joshua B. Fryman , Edward T. Grochowski , Toni Juan , Andrew Thomas Forsyth , John Mejia , Ramacharan Sundararaman , Eric Sprangle , Roger Espasa , Ravi Rajwar
CPC分类号： G06F9/30185 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3861 , G06F12/0817
摘要： In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is predicted. If no contention is predicted, the instruction is executed in the core, and if contention is predicted data associated with the instruction is marshaled and sent to a selected remote agent for execution. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，一种方法包括在处理器核心中接收用于解码的指令，并且基于是否预测争用来动态地处理具有多种行为之一的指令。 如果没有预测到竞争，则在核心中执行指令，并且如果竞争是预测与指令相关联的数据被编组并发送到所选择的远程代理执行。 描述和要求保护其他实施例。
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公开(公告)号：US08145878B2
公开(公告)日：2012-03-27
申请号：US11958225
申请日：2007-12-17
IPC分类号： G06F13/368 , G06F12/10
CPC分类号： G06F12/0284 , G06F2212/206
摘要： A system may comprise one or more source agents, target agents, and a plurality of directory agents, which may determine the target agent to which one or more transactions generated by the source agents is to be sent. A controller may identify one of a plurality of directory agents to process the transactions. The directory agent may determine the control and status registers of the target agents to which the transaction is to be sent. The target agent may complete the transaction after receiving the transaction from the directory agent. The directory agents may store a memory map to resolve the target agent to which the transactions is to be sent. The directory based distributed CSR access may provide scalability to ever increasing number of heterogeneous agents in the system.
摘要翻译： 系统可以包括一个或多个源代理，目标代理和多个目录代理，其可以确定将要发送源代理生成的一个或多个事务的目标代理。 控制器可以识别多个目录代理之一来处理事务。 目录代理可以确定要发送交易的目标代理的控制和状态寄存器。 目标代理可以在从目录代理接收到事务之后完成事务。 目录代理可以存储存储器映射以解析要发送事务的目标代理。 基于目录的分布式CSR访问可以为系统中越来越多的异构代理提供可扩展性。
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公开(公告)号：US09658861B2
公开(公告)日：2017-05-23
申请号：US13993310
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
发明人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
IPC分类号： G06F9/44 , G06F15/177
CPC分类号： G06F9/4405 , G06F15/177
摘要： Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign one of the cores as a boot strap processor (BSP). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned as a BSP or as ineligible to be assigned as the BSP. The initialization logic may detect a last processing core of the plurality of processing cores in the interconnect that is an active processing core based at least in part on the state and is eligible to be assigned as the BSP based at least in part on the attribute. In various embodiments, the initialization information may assign the last processing core as the BSP.
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