公开(公告)号：US08576600B2

公开(公告)日：2013-11-05

申请号：US13420038

申请日：2012-03-14

申请人： Jung Hwan Lee ,  Seong Je Park ,  Ji Hwan Kim ,  Myung Cho ,  Beom Seok Hah

发明人： Jung Hwan Lee ,  Seong Je Park ,  Ji Hwan Kim ,  Myung Cho ,  Beom Seok Hah

IPC分类号： G11C15/00

CPC分类号： G11C15/046 ,  G11C16/10

摘要： A semiconductor memory device includes a memory array configured to include memory cells for storing input data and Code Address Memory (CAM) cells for storing setting data used to set an operation condition; an operation circuit configured to perform a CAM read operation by supplying a read voltage to the CAM cells, perform a test operation for detecting unstable CAM cells in each of which a difference between a threshold voltage and the read voltage is smaller than a permitted limit, from among the CAM cells, and perform an erase operation or a program operation for the unstable CAM cells; and a controller configured to control the operation circuit so that the program operation for storing the setting data in the unstable CAM cells is performed if the number of unstable CAM cells detected in the test operation is greater than a permitted value.

摘要翻译： 半导体存储器件包括：存储器阵列，被配置为包括用于存储输入数据的存储器单元和用于存储用于设置操作条件的设置数据的代码地址存储器（CAM）单元; 配置为通过向CAM单元提供读取电压来执行CAM读取操作的操作电路，执行用于检测阈值电压和读取电压之间的差小于允许极限的不稳定的CAM单元的测试操作， 从CAM单元中进行擦除操作或对不稳定的CAM单元的编程动作; 以及控制器，其被配置为如果在测试操作中检测到​​的不稳定的CAM单元的数量大于允许值，则执行用于将设置数据存储在不稳定的CAM单元中的程序操作。

公开(公告)号：US08456907B2

公开(公告)日：2013-06-04

申请号：US13337196

申请日：2011-12-26

申请人： Ji Hwan Kim ,  Seong Je Park ,  Jung Hwan Lee ,  Myung Cho ,  Beom Seok Hah

发明人： Ji Hwan Kim ,  Seong Je Park ,  Jung Hwan Lee ,  Myung Cho ,  Beom Seok Hah

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/565

摘要： A method of operating a semiconductor memory device includes performing a first program loop including a first program operation and a first verification operation in order to store a lower bit data of n-bit data in memory cells coupled to a page, performing a subprogram loop for memory cells of an erase state, having threshold voltages lower than a target voltage of a negative potential, so that the threshold voltages of the memory cells of the erase state become higher than the target voltage, and performing a second program loop including a second program operation and a second verification operation in order to store an upper bit data of the n-bit data in the memory cells.

摘要翻译： 一种操作半导体存储器件的方法包括执行包括第一程序操作和第一验证操作的第一程序循环，以便将n位数据的低位数据存储在耦合到页面的存储单元中，执行子程序循环 具有低于负电位的目标电压的阈值电压的擦除状态的存储单元，使得擦除状态的存储单元的阈值电压变得高于目标电压，并且执行包括第二程序的第二程序循环 操作和第二验证操作，以便将n位数据的高位数据存储在存储单元中。

公开(公告)号：US07881115B2

公开(公告)日：2011-02-01

申请号：US12471546

申请日：2009-05-26

申请人： Ji Hwan Kim ,  Seong Je Park

发明人： Ji Hwan Kim ,  Seong Je Park

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/3436

摘要： According to a method of programming a nonvolatile memory device, a program operation is performed on a first page by applying a program pulse to the first page. A verification operation is performed on the program operation by applying a verification voltage to the first page. If the program operation for the first page has not been completed, a voltage selected from threshold voltages of the first page is set as a highest threshold voltage. The program operation for the first page is completed by repeatedly performing a program operation and a verification operation on the first page while a voltage level of the program pulse is increased. The sum of a program start voltage for the first page and a difference between the verification voltage and the highest threshold voltage is set as a program start voltage for a second page.

摘要翻译： 根据非易失性存储器件的编程方法，通过向第一页应用编程脉冲，在第一页上执行编程操作。 通过对第一页应用验证电压来对编程操作执行验证操作。 如果第一页的编程操作尚未完成，则从第一页的阈值电压中选择的电压被设置为最高阈值电压。 通过在编程脉冲的电压电平增加的同时在第一页上重复执行编程操作和验证操作来完成第一页的编程操作。 将第一页的程序启动电压和验证电压与最高阈值电压之间的差的和设置为第二页的程序启动电压。

公开(公告)号：US20100182839A1

公开(公告)日：2010-07-22

申请号：US12471546

申请日：2009-05-26

申请人： Ji Hwan Kim ,  Seong Je Park

发明人： Ji Hwan Kim ,  Seong Je Park

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/3436

摘要： According to a method of programming a nonvolatile memory device, a program operation is performed on a first page by applying a program pulse to the first page. A verification operation is performed on the program operation by applying a verification voltage to the first page. If the program operation for the first page has not been completed, a voltage selected from threshold voltages of the first page is set as a highest threshold voltage. The program operation for the first page is completed by repeatedly performing a program operation and a verification operation on the first page while a voltage level of the program pulse is increased. The sum of a program start voltage for the first page and a difference between the verification voltage and the highest threshold voltage is set as a program start voltage for a second page.

摘要翻译： 根据非易失性存储器件的编程方法，通过向第一页应用编程脉冲，在第一页上执行编程操作。 通过对第一页应用验证电压来对编程操作执行验证操作。 如果第一页的编程操作尚未完成，则从第一页的阈值电压中选择的电压被设置为最高阈值电压。 通过在编程脉冲的电压电平增加的同时在第一页上重复执行编程操作和验证操作来完成第一页的编程操作。 将第一页的程序启动电压和验证电压与最高阈值电压之间的差的和设置为第二页的程序启动电压。

公开(公告)号：US08717821B2

公开(公告)日：2014-05-06

申请号：US13244217

申请日：2011-09-23

申请人： Seong Je Park ,  Jung Mi Shin

发明人： Min Joong Jung ,  Seong Je Park

IPC分类号： G11C16/04

CPC分类号： G11C16/3454 ,  G11C16/10 ,  G11C16/3418

摘要： The program method of a nonvolatile memory device includes detecting temperature, setting a step voltage, corresponding to an increment of a program voltage in a program operation of an incremental step pulse program (ISPP) method, wherein the step voltage changes based on the detected temperature, and performing the program operation and a program verification operation based on the set step voltage.

摘要翻译： 非易失性存储器件的编程方法包括在增量步进脉冲程序（ISPP）方法的编程操作中检测对应于编程电压的增量的温度，设定阶梯电压，其中阶跃电压基于检测到的温度而改变 ，并且基于设定的步进电压执行编程操作和程序验证操作。

公开(公告)号：US08264883B2

公开(公告)日：2012-09-11

申请号：US12765230

申请日：2010-04-22

申请人： Kyu Hee Lim ,  Seung Ho Chang ,  Seong Je Park

发明人： Kyu Hee Lim ,  Seung Ho Chang ,  Seong Je Park

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5634 ,  G11C2211/5642

摘要： A semiconductor memory device includes a memory cell array including an even page cell group and an odd page cell group, and a page buffer configured to read data stored in memory cells of the even page cell group and the odd page cell group and store the read data. The page buffer comprises a first latch configured to store first even page data of the even page cell group when a first read operation is performed, a second latch configured to store odd page data of the odd page cell group when a second read operation is performed, and a third latch configured to store second even page data of the even page cell group when a third read operation is performed.

摘要翻译： 一种半导体存储器件包括一个包括偶数页单元组和奇数页单元组的存储单元阵列，以及一个页缓冲器，被配置为读取存储在偶页单元组和奇数页单元组的存储单元中的数据，并存储读 数据。 页面缓冲器包括第一锁存器，其被配置为当执行第一读取操作时存储偶数页单元组的第一偶数页数据;第二锁存器，被配置为当执行第二读取操作时存储奇数页单元组的奇数页数据 以及第三锁存器，被配置为当执行第三读取操作时存储偶数页单元组的第二偶数页数据。

公开(公告)号：US08050098B2

公开(公告)日：2011-11-01

申请号：US12362467

申请日：2009-01-29

申请人： Seong Je Park

发明人： Seong Je Park

IPC分类号： G11C16/04

CPC分类号： G11C16/3454

摘要： A program method of nonvolatile memory devices, which can solve an under program problem by preventing a drop of a verify voltage in the program, and verify operations. According to an aspect of the method, a program operation is performed on a selected memory cell block. Electric charges charged to a channel of memory cell strings included in unselected memory cell blocks are discharged. A verify operation is performed on the selected memory cell block.

摘要翻译： 一种非易失性存储器件的程序方法，其可以通过防止程序中的验证电压下降来解决程序不足问题，并进行验证操作。 根据该方法的一个方面，对所选择的存储器单元块执行编程操作。 充电到未选择的存储单元块中的存储单元串的通道的充电被放电。 对选定的存储单元块执行验证操作。

公开(公告)号：US20100302868A1

公开(公告)日：2010-12-02

申请号：US12790191

申请日：2010-05-28

申请人： Jung Chul Han ,  Seong Je Park

发明人： Jung Chul Han ,  Seong Je Park

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427 ,  G11C16/3454

摘要： A method of operating a nonvolatile memory device, including a memory cell array, which further includes a drain select transistor, a memory cell string, and a source select transistor coupled between a bit line and a source line, where the method includes precharging the bit line, setting the memory cell string in a ground voltage state, coupling the memory cell string and the bit line together and supplying a read voltage or a verification voltage to a selected memory cell of the memory cell string, and coupling the memory cell string and the source line together in order to change a voltage level of the bit line in response to a threshold voltage of the selected memory cell.

摘要翻译： 一种操作包括存储单元阵列的非易失性存储器件的方法，其还包括漏极选择晶体管，存储单元串和耦合在位线和源极线之间的源极选择晶体管，其中所述方法包括对所述位进行预充电 将存储单元串设置为接地电压状态，将存储单元串和位线耦合在一起，并将读取电压或验证电压提供给存储单元串的选定存储单元，并将存储单元串和 源极线一起以响应于所选存储器单元的阈值电压来改变位线的电压电平。

公开(公告)号：US20090285020A1

公开(公告)日：2009-11-19

申请号：US12163946

申请日：2008-06-27

申请人： Seong Je Park ,  Seok Jin Joo

发明人： Seong Je Park ,  Seok Jin Joo

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C2211/5621

摘要： In a method of programming a multi level cell, program speed increases as a program operation/erase operation is repeatedly performed. Particularly, in an ISPP method of reducing a program start voltage, much time may be required to finish a first verifying operation in an initial step where a few program operations/erase operations are performed. Accordingly, a blind verifying method may be applied in accordance with the number of the program operation/erase operations.

摘要翻译： 在编程多电平单元的方法中，程序速度随着重复执行编程操作/擦除操作而增加。 特别地，在减少程序启动电压的ISPP方法中，可能需要很多时间在执行少量编程操作/擦除操作的初始步骤中完成第一验证操作。 因此，可以根据编程操作/擦除操作的次数应用盲验证方法。

公开(公告)号：US07512011B2

公开(公告)日：2009-03-31

申请号：US11771979

申请日：2007-06-29

申请人： Seong Je Park

发明人： Seong Je Park

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C16/0483

摘要： A method of reading data in a non-volatile memory device includes providing a plurality of blocks and a plurality of bit lines, each block having a plurality of memory cells, each block coupled to at least one bit line. First and second bit lines are discharged to be at a low level, the first bit line coupled to a first block, the second bit line coupled to a second block. A read voltage is applied to a first word line coupled to a memory cell to be read in the first block. A pass voltage is applied to a second word line coupled to a memory cell not to be read in the first block. The first bit line coupled to the memory cell to be read is precharged to a high level after applying the read voltage to the first word line and the pass voltage to the second word line. A voltage level of the first bit line is evaluated. Data stored in the memory cell to be read is sensed in accordance with the evaluated voltage level of the first bit line.

摘要翻译： 一种在非易失性存储器件中读取数据的方法包括提供多个块和多个位线，每个块具有多个存储器单元，每个块耦合到至少一个位线。 第一和第二位线被放电到低电平，第一位线耦合到第一块，第二位线耦合到第二块。 读取电压被施加到耦合到要在第一块中读取的存储器单元的第一字线。 通过电压被施加到耦合到在第一块中不被读取的存储器单元的第二字线。 耦合到要读取的存储器单元的第一位线在将读取电压施加到第一字线并将通过电压施加到第二字线之后被预充电到高电平。 评估第一位线的电压电平。 根据第一位线的评估电压电平来感测存储在要读取的存储单元中的数据。