公开(公告)号：US08264883B2

公开(公告)日：2012-09-11

申请号：US12765230

申请日：2010-04-22

申请人： Kyu Hee Lim ,  Seung Ho Chang ,  Seong Je Park

发明人： Kyu Hee Lim ,  Seung Ho Chang ,  Seong Je Park

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5634 ,  G11C2211/5642

摘要： A semiconductor memory device includes a memory cell array including an even page cell group and an odd page cell group, and a page buffer configured to read data stored in memory cells of the even page cell group and the odd page cell group and store the read data. The page buffer comprises a first latch configured to store first even page data of the even page cell group when a first read operation is performed, a second latch configured to store odd page data of the odd page cell group when a second read operation is performed, and a third latch configured to store second even page data of the even page cell group when a third read operation is performed.

摘要翻译： 一种半导体存储器件包括一个包括偶数页单元组和奇数页单元组的存储单元阵列，以及一个页缓冲器，被配置为读取存储在偶页单元组和奇数页单元组的存储单元中的数据，并存储读 数据。 页面缓冲器包括第一锁存器，其被配置为当执行第一读取操作时存储偶数页单元组的第一偶数页数据;第二锁存器，被配置为当执行第二读取操作时存储奇数页单元组的奇数页数据 以及第三锁存器，被配置为当执行第三读取操作时存储偶数页单元组的第二偶数页数据。

公开(公告)号：US20100329014A1

公开(公告)日：2010-12-30

申请号：US12765230

申请日：2010-04-22

申请人： Kyu Hee LIM ,  Seung Ho Chang ,  Seong Je Park

发明人： Kyu Hee LIM ,  Seung Ho Chang ,  Seong Je Park

IPC分类号： G11C16/26 ,  G11C16/04

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5634 ,  G11C2211/5642

摘要： A semiconductor memory device includes a memory cell array including an even page cell group and an odd page cell group, and a page buffer configured to read data stored in memory cells of the even page cell group and the odd page cell group and store the read data. The page buffer comprises a first latch configured to store first even page data of the even page cell group when a first read operation is performed, a second latch configured to store odd page data of the odd page cell group when a second read operation is performed, and a third latch configured to store second even page data of the even page cell group when a third read operation is performed.

摘要翻译： 一种半导体存储器件包括一个包括偶数页单元组和奇数页单元组的存储单元阵列，以及一个页缓冲器，被配置为读取存储在偶页单元组和奇数页单元组的存储单元中的数据，并存储读 数据。 页面缓冲器包括第一锁存器，其被配置为当执行第一读取操作时存储偶数页单元组的第一偶数页数据;第二锁存器，被配置为当执行第二读取操作时存储奇数页单元组的奇数页数据 以及第三锁存器，被配置为当执行第三读取操作时存储偶数页单元组的第二偶数页数据。

公开(公告)号：US20100195400A1

公开(公告)日：2010-08-05

申请号：US12647593

申请日：2009-12-28

申请人： Kyu Hee Lim ,  Seong Je Park ,  Jung Chul Han

发明人： Kyu Hee Lim ,  Seong Je Park ,  Jung Chul Han

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2216/14

摘要： A nonvolatile memory device comprises a page buffer unit, a counter, a program pulse application number storage unit, and a program start voltage setting unit. The page buffer is configured to output a 1-bit pass signal when a cell programmed to exceed a reference voltage, from among target program cells included in a single page, exists. The counter is configured to count a number of program pulses applied to determine a program pulse application number. The program pulse application number storage unit is configured to store a number of program pulses applied until the 1-bit pass signal is received during a program operation for a first page. The program start voltage setting unit is configured to set a program start voltage for a second page based on the stored program pulse application number.

摘要翻译： 非易失性存储器件包括页缓冲器单元，计数器，编程脉冲应用次数存储单元和程序启动电压设置单元。 页缓冲器被配置为当编程为超过包括在单页中的目标程序单元中的参考电压的单元存在时，输出1位通过信号。 计数器配置为对用于确定编程脉冲应用编号的程序脉冲数进行计数。 编程脉冲应用次数存储单元被配置为存储施加的编程脉冲数，直到在第一页的编程操作期间接收到1位通过信号。 程序启动电压设定单元被配置为基于存储的程序脉冲应用程序号来设置第二页的程序启动电压。

公开(公告)号：US08279678B2

公开(公告)日：2012-10-02

申请号：US12764398

申请日：2010-04-21

申请人： Kyu Hee Lim ,  Seong Je Park

发明人： Kyu Hee Lim ,  Seong Je Park

IPC分类号： G11C16/06

CPC分类号： G11C16/3454 ,  G11C16/24

摘要： A method of performing a program verification operation in a nonvolatile memory device includes storing program data, programmed into a selected memory cell of a memory cell block, in a page buffer which is coupled to a bit line of the memory cell block via a sense node, controlling a voltage level of the sense node in response to a value of the program data, changing the voltage level of the sense node in response to a program state of the selected memory cell coupled to the bit line, and performing a program verification operation on the selected memory cell by sensing the voltage level of the sense node.

摘要翻译： 一种在非易失性存储器件中执行程序验证操作的方法包括存储编程到存储器单元块的选定存储单元中的程序数据，该页缓冲器经由检测节点耦合到存储器单元块的位线 响应于所述节目数据的值来控制所述感测节点的电压电平，响应于与所述位线耦合的所选存储器单元的编程状态改变所述感测节点的电压电平，以及执行程序验证操作 通过感测感测节点的电压电平在所选存储单元上。

公开(公告)号：US08174896B2

公开(公告)日：2012-05-08

申请号：US12647593

申请日：2009-12-28

申请人： Kyu Hee Lim ,  Seong Je Park ,  Jung Chul Han

发明人： Kyu Hee Lim ,  Seong Je Park ,  Jung Chul Han

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2216/14

摘要： A nonvolatile memory device comprises a page buffer unit, a counter, a program pulse application number storage unit, and a program start voltage setting unit. The page buffer is configured to output a 1-bit pass signal when a cell programmed to exceed a reference voltage, from among target program cells included in a single page, exists. The counter is configured to count a number of program pulses applied to determine a program pulse application number. The program pulse application number storage unit is configured to store a number of program pulses applied until the 1-bit pass signal is received during a program operation for a first page. The program start voltage setting unit is configured to set a program start voltage for a second page based on the stored program pulse application number.

摘要翻译： 非易失性存储器件包括页缓冲器单元，计数器，编程脉冲应用次数存储单元和程序启动电压设置单元。 页缓冲器被配置为当编程为超过包括在单页中的目标程序单元中的参考电压的单元存在时，输出1位通过信号。 计数器配置为对用于确定编程脉冲应用编号的程序脉冲数进行计数。 编程脉冲应用次数存储单元被配置为存储施加的编程脉冲数，直到在第一页的编程操作期间接收到1位通过信号。 程序启动电压设定单元被配置为基于存储的程序脉冲应用程序号来设置第二页的程序启动电压。

公开(公告)号：US20100332736A1

公开(公告)日：2010-12-30

申请号：US12764520

申请日：2010-04-21

申请人： Kyu Hee LIM ,  Seong Je Park

发明人： Kyu Hee LIM ,  Seong Je Park

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/1032 ,  G06F2212/7202 ,  G11C16/10 ,  G11C16/3431

摘要： A method of programming a nonvolatile memory device comprises storing first data of a first memory block in a page buffer unit, and then programming the first data into a redundant memory block coupled to the page buffer unit, storing second data of a second memory block in the page buffer unit, and then programming the second data into the first memory block, storing third data of a third memory block in the page buffer unit, and then programming the third data into the second memory block, storing the second data of the first memory block in the page buffer unit, and then programming the stored second data into the third memory block, and storing the first data stored in the redundant memory block in the page buffer unit, and then programming the stored first data into the first memory block.

摘要翻译： 一种对非易失性存储器件进行编程的方法包括将第一存储块的第一数据存储在页缓冲器单元中，然后将第一数据编程为耦合到页缓冲器单元的冗余存储器块，将第二存储块的第二数据存储在 页缓冲器单元，然后将第二数据编程到第一存储块中，将第三存储块的第三数据存储在页缓冲器单元中，然后将第三数据编程到第二存储块中，存储第一存储块的第二数据 存储器块，然后将存储的第二数据编程到第三存储器块中，并将存储在冗余存储器块中的第一数据存储在页面缓冲器单元中，然后将存储的第一数据编程到第一存储器块中 。

公开(公告)号：US20100329028A1

公开(公告)日：2010-12-30

申请号：US12764398

申请日：2010-04-21

申请人： Kyu Hee LIM ,  Seong Je Park

发明人： Kyu Hee LIM ,  Seong Je Park

IPC分类号： G11C16/06

CPC分类号： G11C16/3454 ,  G11C16/24

摘要： A method of performing a program verification operation in a nonvolatile memory device includes storing program data, programmed into a selected memory cell of a memory cell block, in a page buffer which is coupled to a bit line of the memory cell block via a sense node, controlling a voltage level of the sense node in response to a value of the program data, changing the voltage level of the sense node in response to a program state of the selected memory cell coupled to the bit line, and performing a program verification operation on the selected memory cell by sensing the voltage level of the sense node.

摘要翻译： 一种在非易失性存储器件中执行程序验证操作的方法包括存储编程到存储器单元块的选定存储单元中的程序数据，该页缓冲器经由检测节点耦合到存储器单元块的位线 响应于所述节目数据的值来控制所述感测节点的电压电平，响应于与所述位线耦合的所选存储器单元的编程状态改变所述感测节点的电压电平，以及执行程序验证操作 通过感测感测节点的电压电平在所选存储单元上。

公开(公告)号：US07379342B2

公开(公告)日：2008-05-27

申请号：US11304433

申请日：2005-12-14

申请人： Seong Je Park ,  Seung Ho Chang

发明人： Seong Je Park ,  Seung Ho Chang

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C16/3454 ,  G11C16/3459

摘要： A program operation and a program verification operation are repeatedly performed. The program verification operation is performed on memory cells including pass cells to obtain a uniform distribution characteristic of a threshold voltage. Furthermore, the program verification operation is performed with a compare voltage being set higher than a target voltage initially so that a threshold voltage of a memory cell is sufficiently higher than the target voltage. The program verification operation is again performed lowering the compare voltage according to the repetition number. Thus, normally programmed cells are prevented from being again excessively programmed.

摘要翻译： 重复执行程序操作和程序验证操作。 在包括通过单元的存储单元上执行程序验证操作，以获得阈值电压的均匀分布特性。 此外，程序验证操作以比初始设定为高于目标电压的比较电压进行，使得存储单元的阈值电压足够高于目标电压。 程序验证操作再次根据重复次数降低比较电压。 因此，防止正常编程的单元被过度编程。

公开(公告)号：US08717821B2

公开(公告)日：2014-05-06

申请号：US13244217

申请日：2011-09-23

申请人： Seong Je Park ,  Jung Mi Shin

发明人： Min Joong Jung ,  Seong Je Park

IPC分类号： G11C16/04

CPC分类号： G11C16/3454 ,  G11C16/10 ,  G11C16/3418

摘要： The program method of a nonvolatile memory device includes detecting temperature, setting a step voltage, corresponding to an increment of a program voltage in a program operation of an incremental step pulse program (ISPP) method, wherein the step voltage changes based on the detected temperature, and performing the program operation and a program verification operation based on the set step voltage.

摘要翻译： 非易失性存储器件的编程方法包括在增量步进脉冲程序（ISPP）方法的编程操作中检测对应于编程电压的增量的温度，设定阶梯电压，其中阶跃电压基于检测到的温度而改变 ，并且基于设定的步进电压执行编程操作和程序验证操作。

公开(公告)号：US08050098B2

公开(公告)日：2011-11-01

申请号：US12362467

申请日：2009-01-29

申请人： Seong Je Park

发明人： Seong Je Park

IPC分类号： G11C16/04

CPC分类号： G11C16/3454

摘要： A program method of nonvolatile memory devices, which can solve an under program problem by preventing a drop of a verify voltage in the program, and verify operations. According to an aspect of the method, a program operation is performed on a selected memory cell block. Electric charges charged to a channel of memory cell strings included in unselected memory cell blocks are discharged. A verify operation is performed on the selected memory cell block.

摘要翻译： 一种非易失性存储器件的程序方法，其可以通过防止程序中的验证电压下降来解决程序不足问题，并进行验证操作。 根据该方法的一个方面，对所选择的存储器单元块执行编程操作。 充电到未选择的存储单元块中的存储单元串的通道的充电被放电。 对选定的存储单元块执行验证操作。