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    Integrated circuit with multiple spacer insulating region widths
    1.
    发明授权
    Integrated circuit with multiple spacer insulating region widths 有权
    具有多个间隔绝缘区域宽度的集成电路

    公开(公告)号：US07064396B2

    公开(公告)日：2006-06-20

    申请号：US10790420

    申请日：2004-03-01

    申请人： Jian Chen ,  Vance H. Adams ,  Choh-Fei Yeap

    发明人： Jian Chen ,  Vance H. Adams ,  Choh-Fei Yeap

    IPC分类号： H01L29/94 ,  H01L31/062

    CPC分类号： H01L21/823864 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203

    摘要： An integrated circuit with both P-channel transistors (823) and N-channel transistors (821) with different spacer insulating region widths. In one example, the outer sidewall spacer (321) of the N-channel transistors is removed while the P-channel regions (115) are masked such that the spacer insulating region widths of the N-channel transistors is less than the spacer insulating region widths of the P-channel transistors. Also, the drain/source silicide regions (805) of the N-channel transistors are located closer to the gates (117) of those transistors than the P-channel source/drain suicide regions (809) are located to the gates (119) of those transistors. Providing the P-channel transistors with greater spacer insulating widths and greater distances between the source/drain silicide regions and gates may increase the relative compressive stress of the channel region of the P-channel transistors relative the stress of the channel region of the N-channel transistors, thereby increasing the performance of the P-channel transistors.

    摘要翻译： 具有不同间隔绝缘区宽度的具有P沟道晶体管（823）和N沟道晶体管（821）的集成电路。 在一个示例中，除去N沟道晶体管的外侧壁间隔物（321），同时P沟道区域（115）被掩蔽，使得N沟道晶体管的间隔绝缘区域宽度小于间隔绝缘区域 P沟道晶体管的宽度。 此外，N沟道晶体管的漏极/源极硅化物区域（805）位于比P沟道源极/漏极硅化物区域（809）位于栅极（119）处更靠近那些晶体管的栅极（117） 的晶体管。 在源/漏硅化物区域和栅极之间提供具有较大间隔绝缘宽度和较大距离的P沟道晶体管可以增加P沟道晶体管的沟道区相对于N沟道晶体管的沟道区的应力的相对压缩应力， 通道晶体管，从而增加P沟道晶体管的性能。

    Transistor structure with stress modification and capacitive reduction feature in a channel direction and method thereof
    3.
    发明申请
    Transistor structure with stress modification and capacitive reduction feature in a channel direction and method thereof 审中-公开
    具有应力改变和通道方向的电容降低特性的晶体管结构及其方法

    公开(公告)号：US20060043500A1

    公开(公告)日：2006-03-02

    申请号：US10925057

    申请日：2004-08-24

    申请人： Jian Chen ,  Michael Mendicino ,  Vance Adams ,  Choh-Fei Yeap ,  Venkat Kolagunta

    发明人： Jian Chen ,  Michael Mendicino ,  Vance Adams ,  Choh-Fei Yeap ,  Venkat Kolagunta

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/78 ,  H01L29/7843

    摘要： A transistor comprises an active region having a periphery with opposing sides and a source and a drain positioned within the active region. A gate overlies a channel area of the active region, the channel region separating the source and drain. The transistor further includes at least one stress modifying feature extending from an edge of the active region on at least one of a source side or a drain side and toward the channel area but not entering the channel area. The at least one stress modifying feature includes a dielectric.

    摘要翻译： 晶体管包括具有相对侧边缘的有源区和位于有源区内的源极和漏极。 A栅极覆盖有源区的沟道区，沟道区分离源极和漏极。 晶体管还包括至少一个应力调整特征，其从源极侧或漏极侧中的至少一个上方的有源区域的边缘延伸并且朝向沟道区域而不进入沟道区域。 所述至少一个应力改变特征包括电介质。

    Integrated circuit with multiple spacer insulating region widths
    4.
    发明申请
    Integrated circuit with multiple spacer insulating region widths 审中-公开
    具有多个间隔绝缘区域宽度的集成电路

    公开(公告)号：US20060011988A1

    公开(公告)日：2006-01-19

    申请号：US11231087

    申请日：2005-09-20

    申请人： Jian Chen ,  Vance Adams ,  Choh-Fei Yeap

    发明人： Jian Chen ,  Vance Adams ,  Choh-Fei Yeap

    IPC分类号： H01L29/94

    CPC分类号： H01L21/823864 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203

    摘要： An integrated circuit with both P-channel transistors (823) and N-channel transistors (821) with different spacer insulating region widths. In one example, the outer sidewall spacer (321) of the N-channel transistors is removed while the P-channel regions (115) are masked such that the spacer insulating region widths of the N-channel transistors is less than the spacer insulating region widths of the P-channel transistors. Also, the drain/source silicide regions (805) of the N-channel transistors are located closer to the gates (117) of those transistors than the P-channel source/drain silicide regions (809) are located to the gates (119) of those transistors. Providing the P-channel transistors with greater spacer insulating widths and greater distances between the source/drain silicide regions and gates may increase the relative compressive stress of the channel region of the P-channel transistors relative the stress of the channel region of the N-channel transistors, thereby increasing the performance of the P-channel transistors.

    摘要翻译： 具有不同间隔绝缘区宽度的具有P沟道晶体管（823）和N沟道晶体管（821）的集成电路。 在一个示例中，除去N沟道晶体管的外侧壁间隔物（321），同时P沟道区域（115）被掩蔽，使得N沟道晶体管的间隔绝缘区域宽度小于间隔绝缘区域 P沟道晶体管的宽度。 此外，N沟道晶体管的漏极/源极硅化物区域（805）位于比P沟道源极/漏极硅化物区域（809）位于栅极（119）处更靠近那些晶体管的栅极（117） 的晶体管。 在源/漏硅化物区域和栅极之间提供具有较大间隔绝缘宽度和较大距离的P沟道晶体管可以增加P沟道晶体管的沟道区相对于N沟道晶体管的沟道区的应力的相对压缩应力， 通道晶体管，从而增加P沟道晶体管的性能。

    Method for forming trench isolation
    5.
    发明授权
    Method for forming trench isolation 失效

    公开(公告)号：US06503814B2

    公开(公告)日：2003-01-07

    申请号：US09765740

    申请日：2001-01-19

    申请人： Choh-Fei Yeap ,  Jian Chen ,  Franklin D. Nkansah

    发明人： Choh-Fei Yeap ,  Jian Chen ,  Franklin D. Nkansah

    IPC分类号： H01L2176

    CPC分类号： H01L21/76237

    摘要： The semiconductor device has a trench isolation between a P-well and N-well. This trench isolation region is formed of oxide which during the course of the formation of the P and N well is doped with P-type and N-type dopants. Thus the trench has a P-type doped region and an N-type doped region which are typically phosphorous and boron. After the P and N well are formed, a rapid thermal anneal is applied to the device structure. This has the effect of causing the phosphorous doped and boron doped portions of the trench oxide to be etched at substantially the same rate. After this RTA step, gate oxide is formed over the P and N well. The following formation of polysilicon gates results in a relatively flat gate over transistor structure. This avoids corner leakage which is a problem with trench isolation.

    Integrated circuit with multiple spacer insulating region widths
    7.
    发明申请
    Integrated circuit with multiple spacer insulating region widths 有权
    具有多个间隔绝缘区域宽度的集成电路

    公开(公告)号：US20050190421A1

    公开(公告)日：2005-09-01

    申请号：US10790420

    申请日：2004-03-01

    申请人： Jian Chen ,  Vance Adams ,  Choh-Fei Yeap

    发明人： Jian Chen ,  Vance Adams ,  Choh-Fei Yeap

    IPC分类号： G02B26/08 ,  H01L21/84 ,  H01L27/12

    CPC分类号： H01L21/823864 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203

    摘要： An integrated circuit with both P-channel transistors (823) and N-channel transistors (821) with different spacer insulating region widths. In one example, the outer sidewall spacer (321) of the N-channel transistors is removed while the P-channel regions (115) are masked such that the spacer insulating region widths of the N-channel transistors is less than the spacer insulating region widths of the P-channel transistors. Also, the drain/source silicide regions (805) of the N-channel transistors are located closer to the gates (117) of those transistors than the P-channel source/drain suicide regions (809) are located to the gates (119) of those transistors. Providing the P-channel transistors with greater spacer insulating widths and greater distances between the source/drain silicide regions and gates may increase the relative compressive stress of the channel region of the P-channel transistors relative the stress of the channel region of the N-channel transistors, thereby increasing the performance of the P-channel transistors.

    摘要翻译： 具有不同间隔绝缘区宽度的具有P沟道晶体管（823）和N沟道晶体管（821）的集成电路。 在一个示例中，除去N沟道晶体管的外侧壁间隔物（321），同时P沟道区域（115）被掩蔽，使得N沟道晶体管的间隔绝缘区域宽度小于间隔绝缘区域 P沟道晶体管的宽度。 此外，N沟道晶体管的漏极/源极硅化物区域（805）位于比P沟道源极/漏极硅化物区域（809）位于栅极（119）处更靠近那些晶体管的栅极（117） 的晶体管。 在源/漏硅化物区域和栅极之间提供具有较大间隔绝缘宽度和较大距离的P沟道晶体管可以增加P沟道晶体管的沟道区相对于N沟道晶体管的沟道区的应力的相对压缩应力， 通道晶体管，从而增加P沟道晶体管的性能。

    Semiconductor fabrication process using transistor spacers of differing widths
    8.
    发明授权
    Semiconductor fabrication process using transistor spacers of differing widths 有权
    使用不同宽度的晶体管间隔物的半导体制造工艺

    公开(公告)号：US06864135B2

    公开(公告)日：2005-03-08

    申请号：US10285374

    申请日：2002-10-31

    申请人： Paul A. Grudowski ,  Jian Chen ,  Choh-Fei Yeap

    发明人： Paul A. Grudowski ,  Jian Chen ,  Choh-Fei Yeap

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/49

    CPC分类号： H01L29/4983 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659

    摘要： A semiconductor fabrication process is disclosed wherein a first gate (108, 114) is formed over a first portion of a semiconductor substrate (102) and a second gate (114, 108) is formed over a second portion of the substrate (102). A spacer film (118) is deposited over substrate (102) and first and second gates (108, 114). First spacers (126) are then formed on sidewalls of the second gate (114) and second spacers (136) are formed on sidewalls of first gate (108). The first and second spacers (126, 136) have different widths. The process may further include forming first source/drain regions (128) in the substrate laterally disposed on either side of the first spacers (126) and second source/drain regions (138) are formed on either side of second spacers (136). The different spacer widths may be achieved using masked first and second spacer etch processes (125, 135) having different degrees of isotropy. The spacer etch mask and the source/drain implant mask may be common such that p-channel transistors have a different spacer width than n-channel transistors.

    摘要翻译： 公开了半导体制造工艺，其中第一栅极（108,114）形成在半导体衬底（102）的第一部分上，并且在衬底（102）的第二部分上方形成第二栅极（114,108）。 间隔膜（118）沉积在衬底（102）和第一和第二栅极（108,114）上。 然后在第二栅极（114）的侧壁上形成第一间隔物（126），并且第二间隔物（136）形成在第一栅极（108）的侧壁上。 第一和第二间隔物（126,136）具有不同的宽度。 该工艺可以进一步包括在横向设置在第一间隔物（126）的任一侧上的衬底中形成第一源极/漏极区（128），并且在第二间隔物（136）的任一侧上形成第二源/漏区（138）。 可以使用具有不同程度的各向同性的掩蔽的第一和第二间隔物蚀刻工艺（125,135）来实现不同的间隔物宽度。 间隔物蚀刻掩模和源极/漏极注入掩模可以是共同的，使得p沟道晶体管具有与n沟道晶体管不同的间隔物宽度。

    Step-stool
    9.
    外观设计
    Step-stool 有权

    公开(公告)号：USD1008676S1

    公开(公告)日：2023-12-26

    申请号：US29820654

    申请日：2021-12-23

    申请人： Jian Chen

    设计人： Jian Chen

    摘要： FIG. 1 is a perspective view of a step-stool showing my new design;
    FIG. 2 is a front view thereof;
    FIG. 3 is a rear view thereof;
    FIG. 4 is a left side view thereof;
    FIG. 5 is a right side view thereof;
    FIG. 6 is a top view thereof;
    FIG. 7 is a bottom view thereof;
    FIG. 8 is a bottom side perspective view thereof; and,
    FIG. 9 is a perspective view of the step-stool of FIG. 1, shown with unclaimed patterned ornamentation.
    The broken lines in the drawings depict portions of the step-stool that form no part of the claimed design.

    Shock Tube and Cell Electroporation Device with the Shock Tube
    10.
    发明申请
    Shock Tube and Cell Electroporation Device with the Shock Tube 审中-公开

    公开(公告)号：US20200032191A1

    公开(公告)日：2020-01-30

    申请号：US16586989

    申请日：2019-09-29

    申请人： Jian Chen

    发明人： Jian Chen

    IPC分类号： C12M1/42 ,  C12M1/12 ,  B01L3/00

    摘要： The shock tube comprises a tube, a first electrode, a second electrode and a stopple, wherein the tube is internally provided with a cavity for accommodating a target liquid sample. The first electrode is arranged at one end of the tube. The second electrode is arranged in the stopple, and the outer end of the second electrode can be electrically connected with the exterior via an opening of the stopple. The stopple is internally provided with an elastic piece connected with the second electrode. The outer side of the elastic piece is connected with the stopple, and the inner side of the elastic piece is connected with the second electrode. The invention further provides a cell electroporation device where the shock tube can be placed.