公开(公告)号：US07843011B2

公开(公告)日：2010-11-30

申请号：US11669794

申请日：2007-01-31

申请人： Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

发明人： Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

IPC分类号： H01L27/092

CPC分类号： H01L27/1203 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/3143 ,  H01L21/3185 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/78 ,  H01L29/7843

摘要： An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.

摘要翻译： 电子设备可以包括场隔离区域和具有第一应变的第一绝缘层，并且具有从顶视图完全位于场隔离区域内的部分。 电子器件还可以包括具有不同于第一应变的第二应变并且包括开口的第二绝缘层。 从顶视图，第一绝缘层的部分可以位于第二绝缘层的开口内。 在一个实施例中，场隔离区域可以包括虚拟结构，并且第一绝缘层的部分可以覆盖虚拟结构。 形成电子器件的过程可以包括形成绝缘层的岛部，其中从顶视图看，岛部完全位于场隔离区内。

公开(公告)号：US07678698B2

公开(公告)日：2010-03-16

申请号：US11744581

申请日：2007-05-04

申请人： Xiangzheng Bo ,  Tien Ying Luo ,  Kurt H. Junker ,  Paul A. Grudowski ,  Venkat R. Kolagunta

发明人： Xiangzheng Bo ,  Tien Ying Luo ,  Kurt H. Junker ,  Paul A. Grudowski ,  Venkat R. Kolagunta

IPC分类号： H01L21/44

CPC分类号： H01L29/7843 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/3185 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.

摘要翻译： 半导体器件具有至少两个用UV辐射固化的拉伸应力层。 在第一应力层之后形成第二拉伸应力层。 在一些实例中，拉伸应力层包括氮化硅和氢。 在一些实例中，第二拉伸应力层由于固化而比第一拉伸应力层具有更大的收缩率。 在一种形式中，固化后的第二张应力层比第一拉伸应力层具有更大的拉伸应力。 拉伸应力层用于改善N沟道晶体管中的载流子迁移率，从而提高晶体管性能。 在一种形式中，提供单组上覆的拉伸应力层，每层越来越厚，并且在固化之前具有越来越多的氢。 在其它实施方案中，形成多个重叠的基团，每个基团具有相似的重复深度和氢分布。

公开(公告)号：US07560318B2

公开(公告)日：2009-07-14

申请号：US11374372

申请日：2006-03-13

申请人： Mariam G. Sadaka ,  Venkat R. Kolagunta ,  William J. Taylor ,  Victor H. Vartanian

发明人： Mariam G. Sadaka ,  Venkat R. Kolagunta ,  William J. Taylor ,  Victor H. Vartanian

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L21/76256 ,  H01L27/1203 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78687

摘要： An electronic device can have an insulating layer lying between a first semiconductor layer and a base layer. A second semiconductor layer, having a different composition and stress as compared to the first semiconductor layer, can overlie at least a portion of the first semiconductor layer. In one embodiment, a first electronic component can include a first active region that includes a first portion of the first and the second semiconductor layers. A second electronic component can include a second active region that can include a second portion of the first semiconductor layer. Different processes can be used to form the electronic device. In another embodiment, annealing a workpiece can be performed and the stress of at least one of the semiconductor layers can be changed. In a different embodiment, annealing the workpiece can be performed either before or after the formation of the second semiconductor layer.

摘要翻译： 电子设备可以具有位于第一半导体层和基底层之间的绝缘层。 与第一半导体层相比具有不同组成和应力的第二半导体层可以覆盖在第一半导体层的至少一部分上。 在一个实施例中，第一电子部件可以包括第一有源区，其包括第一和第二半导体层的第一部分。 第二电子部件可以包括可以包括第一半导体层的第二部分的第二有源区。 可以使用不同的过程来形成电子设备。 在另一个实施例中，可以执行退火工件，并且可以改变至少一个半导体层的应力。 在不同的实施例中，退火工件可以在第二半导体层的形成之前或之后进行。

公开(公告)号：US07504289B2

公开(公告)日：2009-03-17

申请号：US11258781

申请日：2005-10-26

申请人： Sangwoo Lim ,  Stanley L. Filipiak ,  Paul A. Grudowski ,  Venkat R. Kolagunta

发明人： Sangwoo Lim ,  Stanley L. Filipiak ,  Paul A. Grudowski ,  Venkat R. Kolagunta

IPC分类号： H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/7843

摘要： An electronic device can include a first transistor structure including a first gate electrode surrounded by a first sidewall spacer having a first stress and a second transistor structure including a second gate electrode surrounding a second sidewall spacer having second stress. The first sidewall spacer is an only sidewall spacer surrounding the first gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the first gate electrode and the second sidewall spacer is an only sidewall spacer surrounding the second gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the second gate electrode, wherein the first stress has a lower value as compared to the second stress. More than one process can be used to form the electronic device.

摘要翻译： 电子器件可以包括第一晶体管结构，其包括由具有第一应力的第一侧壁间隔物围绕的第一栅电极和包括围绕具有第二应力的第二侧壁间隔物的第二栅电极的第二晶体管结构。 与围绕第一栅电极的任何其它侧壁间隔物相比，第一侧壁间隔物是围绕第一栅电极或更靠近的侧壁间隔物的唯一侧壁间隔物，并且第二侧壁间隔物是仅围绕第二栅电极的侧壁间隔物 与围绕第二栅电极的任何其它侧壁间隔物相比，其中第一应力具有与第二应力相比较低的值。 可以使用多个过程来形成电子设备。

公开(公告)号：US07282426B2

公开(公告)日：2007-10-16

申请号：US11092289

申请日：2005-03-29

申请人： Leo Mathew ,  Venkat R. Kolagunta ,  David C. Sing

发明人： Leo Mathew ,  Venkat R. Kolagunta ,  David C. Sing

IPC分类号： H01L21/425

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/78624 ,  H01L2924/0002 ,  Y10S438/981 ,  H01L2924/00

摘要： A method for forming a semiconductor device including forming a semiconductor substrate; forming a gate electrode over the semiconductor substrate having a first side and a second side, and forming a gate dielectric under the gate electrode. The gate dielectric has a first area under the gate electrode and adjacent the first side of the gate electrode, a second area under the gate electrode and adjacent the second side of the gate electrode, and a third area under the gate electrode that is between the first area and the second area, wherein the first area is thinner than the second area, and the third area is thinner than the first area and is thinner than the second area.

摘要翻译： 一种形成半导体器件的方法，包括形成半导体衬底; 在具有第一侧和第二侧的半导体衬底上形成栅电极，以及在栅极下形成栅极电介质。 栅极电介质具有栅电极下方的第一区域，并且与栅电极的第一侧相邻，第二区域在栅电极下方并且邻近栅电极的第二侧，栅极下方的第三区域位于栅电极之间 第一区域和第二区域，其中第一区域比第二区域薄，第三区域比第一区域薄，并且比第二区域薄。

公开(公告)号：US08021957B2

公开(公告)日：2011-09-20

申请号：US12883096

申请日：2010-09-15

申请人： Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

发明人： Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

IPC分类号： H01L21/76

CPC分类号： H01L27/1203 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/3143 ,  H01L21/3185 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/78 ,  H01L29/7843

摘要： An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.

摘要翻译： 电子设备可以包括场隔离区域和具有第一应变的第一绝缘层，并且具有从顶视图完全位于场隔离区域内的部分。 电子器件还可以包括具有不同于第一应变的第二应变并且包括开口的第二绝缘层。 从顶视图，第一绝缘层的部分可以位于第二绝缘层的开口内。 在一个实施例中，场隔离区域可以包括虚拟结构，并且第一绝缘层的部分可以覆盖虚拟结构。 形成电子器件的过程可以包括形成绝缘层的岛部，其中从顶视图看，岛部完全位于场隔离区内。

公开(公告)号：US20090042351A1

公开(公告)日：2009-02-12

申请号：US11835547

申请日：2007-08-08

申请人： Xiangzheng Bo ,  Venkat R. Kolagunta ,  Konstantin V. Loiko

发明人： Xiangzheng Bo ,  Venkat R. Kolagunta ,  Konstantin V. Loiko

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833

摘要： A method for forming a semiconductor device on a semiconductor material layer includes forming a gate structure over the semiconductor material layer. The method further includes forming a first nitride spacer adjacent to the gate structure and forming source/drain extensions in the semiconductor material layer. The method further includes forming an oxide liner overlying the gate structure and the source/drain extensions. The method further includes forming a second nitride spacer adjacent to the oxide liner. The method further includes forming source/drain regions in the semiconductor material layer. The method further includes using an etching process that is selective to the oxide liner, removing the second nitride spacer. The method further includes using an etching process that is selective to the first nitride spacer, at least partially removing the oxide liner. The method further includes forming silicide regions overlying the source/drain regions and the gate structure.

摘要翻译： 在半导体材料层上形成半导体器件的方法包括在半导体材料层上形成栅极结构。 该方法还包括形成邻近栅极结构的第一氮化物间隔区，并在半导体材料层中形成源极/漏极延伸部分。 该方法还包括形成覆盖栅极结构和源极/漏极延伸部的氧化物衬垫。 该方法还包括在氧化物衬垫附近形成第二氮化物间隔物。 该方法还包括在半导体材料层中形成源极/漏极区域。 该方法还包括使用对氧化物衬垫有选择性的蚀刻工艺，去除第二氮化物间隔物。 该方法还包括使用对第一氮化物间隔物具有选择性的蚀刻工艺，至少部分地去除氧化物衬垫。 该方法还包括形成覆盖源极/漏极区域和栅极结构的硅化物区域。

公开(公告)号：US20080272411A1

公开(公告)日：2008-11-06

申请号：US11744581

申请日：2007-05-04

申请人： Xiangzheng Bo ,  Tien Ying Luo ,  Kurt H. Junker ,  Paul A. Grudowski ,  Venkat R. Kolagunta

发明人： Xiangzheng Bo ,  Tien Ying Luo ,  Kurt H. Junker ,  Paul A. Grudowski ,  Venkat R. Kolagunta

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L29/7843 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/3185 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.

摘要翻译： 半导体器件具有至少两个用UV辐射固化的拉伸应力层。 在第一应力层之后形成第二拉伸应力层。 在一些实例中，拉伸应力层包括氮化硅和氢。 在一些实例中，第二拉伸应力层由于固化而比第一拉伸应力层具有更大的收缩率。 在一种形式中，固化后的第二拉伸应力层比第一拉伸应力层具有更大的拉伸应力。 拉伸应力层用于改善N沟道晶体管中的载流子迁移率，从而提高晶体管性能。 在一种形式中，提供单组上覆的拉伸应力层，每层越来越厚，并且在固化之前具有越来越多的氢。 在其它实施方案中，形成多个重叠的基团，每个基团具有相似的重复深度和氢分布。

公开(公告)号：US20080261362A1

公开(公告)日：2008-10-23

申请号：US11737496

申请日：2007-04-19

申请人： Da Zhang ,  Xiangzheng Bo ,  Venkat R. Kolagunta

发明人： Da Zhang ,  Xiangzheng Bo ,  Venkat R. Kolagunta

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having a second sidewall spacer. The method further includes forming a liner and forming a tensile stressor layer over the liner and removing a portion of the tensile stressor layer from a region overlying the p-channel device. The method further includes transferring a stress characteristic of an overlying portion of a remaining portion of the tensile stressor layer to a channel of the n-channel device. The method further includes using the remaining portion of the tensile stressor layer as a hard mask, forming a first recess and a second recess adjacent the gate of the p-channel device.

摘要翻译： 一种用于形成半导体器件的方法包括提供衬底并形成p沟道器件和n沟道器件，每个p沟道器件和n沟道器件包括源极，漏极和栅极， p沟道器件具有第一侧壁间隔物，并且所述n沟道器件具有第二侧壁间隔物。 该方法还包括形成衬套并在衬套上形成拉伸应力层，并从覆盖p沟道器件的区域去除拉伸应力层的一部分。 该方法还包括将拉伸应力层的剩余部分的上覆部分的应力特性转移到n沟道器件的通道。 该方法还包括使用拉伸应力层的剩余部分作为硬掩模，形成邻近p沟道器件的栅极的第一凹槽和第二凹槽。

公开(公告)号：US20080261355A1

公开(公告)日：2008-10-23

申请号：US11737492

申请日：2007-04-19

申请人： Sinan Goktepeli ,  Venkat R. Kolagunta

发明人： Sinan Goktepeli ,  Venkat R. Kolagunta

IPC分类号： H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/84 ,  H01L29/665 ,  H01L29/6653

摘要： First and second transistors are formed adjacent to each other. Both transistors have gate sidewall spacers removed. A stressor layer is formed overlying the first and second transistors. Stress in the stressor layer that overlies the first transistor is modified. Stress in the stressor layer that overlies the second transistor is permanently transferred to a channel of the second transistor. The stressor layer is removed except adjacent the gate electrode sidewalls of the first transistor and the second transistor where the stressor layer is used as gate sidewall spacers. Electrical contact to electrodes of the first transistor and the second transistor is made while using the gate sidewall spacers for determining a physical boundary of current electrodes of the first and second transistors. Subsequently formed first and a second stressors are positioned close to transistor channels of the first and second transistors.

摘要翻译： 第一和第二晶体管彼此相邻地形成。 两个晶体管都有去除栅侧壁间隔。 形成覆盖第一和第二晶体管的应力层。 改变了位于第一晶体管上的应力层的应力。 覆盖在第二晶体管上的应力层的应力永久地转移到第二晶体管的沟道。 去除应力源层，除了邻近第一晶体管的栅电极侧壁和应力层用作栅极侧壁间隔物的第二晶体管。 在使用用于确定第一和第二晶体管的电流电极的物理边界的栅极侧壁间隔物的同时，进行与第一晶体管和第二晶体管的电极的电接触。 随后形成第一和第二应力源靠近第一和第二晶体管的晶体管通道。