公开(公告)号：US08021957B2

公开(公告)日：2011-09-20

申请号：US12883096

申请日：2010-09-15

Applicant: Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

Inventor： Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

IPC: H01L21/76

CPC classification number: H01L27/1203 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/3143 ,  H01L21/3185 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/78 ,  H01L29/7843

Abstract: An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.

Abstract translation: 电子设备可以包括场隔离区域和具有第一应变的第一绝缘层，并且具有从顶视图完全位于场隔离区域内的部分。 电子器件还可以包括具有不同于第一应变的第二应变并且包括开口的第二绝缘层。 从顶视图，第一绝缘层的部分可以位于第二绝缘层的开口内。 在一个实施例中，场隔离区域可以包括虚拟结构，并且第一绝缘层的部分可以覆盖虚拟结构。 形成电子器件的过程可以包括形成绝缘层的岛部，其中从顶视图看，岛部完全位于场隔离区内。

公开(公告)号：US07528029B2

公开(公告)日：2009-05-05

申请号：US11408347

申请日：2006-04-21

Applicant: Paul A. Grudowski ,  Darren V. Goedekc ,  John J. Hackenberg

Inventor： Paul A. Grudowski ,  Darren V. Goedekc ,  John J. Hackenberg

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for making a semiconductor device. In accordance with the method, a substrate (203) is provided which has first (205) and second (207) gate structures thereon. A first stressor layer (215) is formed over the substrate, and a sacrificial layer (216) is formed over the first stressor layer. A second stressor layer (219) is formed over the sacrificial layer.

Abstract translation: 提供了制造半导体器件的方法。 根据该方法，提供在其上具有第一（205）和第二（207）门结构的衬底（203）。 第一应力层（215）形成在衬底上，牺牲层（216）形成在第一应激层上。 在牺牲层上形成第二应力层（219）。

公开(公告)号：US20080272411A1

公开(公告)日：2008-11-06

申请号：US11744581

申请日：2007-05-04

Applicant: Xiangzheng Bo ,  Tien Ying Luo ,  Kurt H. Junker ,  Paul A. Grudowski ,  Venkat R. Kolagunta

Inventor： Xiangzheng Bo ,  Tien Ying Luo ,  Kurt H. Junker ,  Paul A. Grudowski ,  Venkat R. Kolagunta

IPC: H01L29/78 ,  H01L21/3205

CPC classification number: H01L29/7843 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/3185 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.

Abstract translation: 半导体器件具有至少两个用UV辐射固化的拉伸应力层。 在第一应力层之后形成第二拉伸应力层。 在一些实例中，拉伸应力层包括氮化硅和氢。 在一些实例中，第二拉伸应力层由于固化而比第一拉伸应力层具有更大的收缩率。 在一种形式中，固化后的第二拉伸应力层比第一拉伸应力层具有更大的拉伸应力。 拉伸应力层用于改善N沟道晶体管中的载流子迁移率，从而提高晶体管性能。 在一种形式中，提供单组上覆的拉伸应力层，每层越来越厚，并且在固化之前具有越来越多的氢。 在其它实施方案中，形成多个重叠的基团，每个基团具有相似的重复深度和氢分布。

公开(公告)号：US06902971B2

公开(公告)日：2005-06-07

申请号：US10624203

申请日：2003-07-21

Applicant: Paul A. Grudowski

Inventor： Paul A. Grudowski

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L21/823468 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842

Abstract: A semiconductor fabrication process and the resulting integrated circuit include forming a gate electrode (116) over a gate dielectric (104) over a semiconductor substrate (102). A spacer film (124) exhibiting a tensile stress characteristic is deposited over the gate electrode (116). The stress characteristics of at least a portion of the spacer film is then modulated (132, 192) and the spacer film (124) is etched to form sidewall spacers (160, 162) on the gate electrode sidewalls. The spacer film (124) is an LPCVD silicon nitride in one embodiment. Modulating (132) the spacer film (124) includes implanting Xenon or Germanium into the spacers (160) at an implant energy sufficient to break at least some of the silicon nitride bonds. The modulation implant (132) may be performed selectively or non-selectively either before or after etching the spacer film (124).

公开(公告)号：US06369430B1

公开(公告)日：2002-04-09

申请号：US09823310

申请日：2001-04-02

Applicant: Olubunmi O. Adetutu ,  Yeong-Jyh T. Lii ,  Paul A. Grudowski

Inventor： Olubunmi O. Adetutu ,  Yeong-Jyh T. Lii ,  Paul A. Grudowski

IPC: H01L2976

CPC classification number: H01L21/76831 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475

Abstract: Insulating layers between transistors that are very close together may have voids. When contacts are formed in these areas between these close transistors, the contact hole is formed at the void location. These voids may extend between the contact locations that are close together so that the deposition of the conductive material into these contact holes may extend sufficiently into the void to short two such contacts. This is prevented by placing a liner in the contact hole, which constricts the void size in the contact hole, prior to depositing the conductive material. This restricts ingress of conductive material into the void. This prevents the void from being an unwanted conduction path between two contacts that are in close proximity. The bottoms of the contact holes are etched to remove the liner prior to depositing the conductive material.

Abstract translation: 非常靠近在一起的晶体管之间的绝缘层可能具有空隙。 当在这些紧密晶体管之间的这些区域中形成接触时，在空隙位置处形成接触孔。 这些空隙可以在靠近在一起的接触位置之间延伸，使得导电材料沉积到这些接触孔中可以充分地延伸到空隙中以短两个这样的接触。 在沉积导电材料之前，通过将衬垫放置在接触孔中来限制接触孔中的空隙尺寸来防止这种情况。 这限制了导电材料进入空隙。 这样可以防止这两个触点之间的不必要的导电路径的空隙处于非常接近的位置。 在沉积导电材料之前蚀刻接触孔的底部以去除衬垫。

公开(公告)号：US08569858B2

公开(公告)日：2013-10-29

申请号：US11613326

申请日：2006-12-20

Applicant: Brian A. Winstead ,  Vance H. Adams ,  Paul A. Grudowski

Inventor： Brian A. Winstead ,  Vance H. Adams ,  Paul A. Grudowski

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/0642 ,  H01L21/823412 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849

Abstract: An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.

Abstract translation: 集成电路包括包括器件的有源区的器件，其中器件的有源区包括具有横向和横向方向的沟道区。 器件还包括与有源区相邻的有源区的隔离区，该隔离区位于有源区域的横向方向，其中隔离区域包括位于与沟道区域横向的第一区域。 隔离区域还包括位于从第一区域的横向方向上的第二区域。 隔离区域的第一区域处于第一类型的应力处，并且隔离区域的第二区域是在第一类型的较小应力下或在与第一类型相反的第二类型的应力下。

公开(公告)号：US07843011B2

公开(公告)日：2010-11-30

申请号：US11669794

申请日：2007-01-31

Applicant: Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

Inventor： Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

IPC: H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/3143 ,  H01L21/3185 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/78 ,  H01L29/7843

Abstract: An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.

Abstract translation: 电子设备可以包括场隔离区域和具有第一应变的第一绝缘层，并且具有从顶视图完全位于场隔离区域内的部分。 电子器件还可以包括具有不同于第一应变的第二应变并且包括开口的第二绝缘层。 从顶视图，第一绝缘层的部分可以位于第二绝缘层的开口内。 在一个实施例中，场隔离区域可以包括虚拟结构，并且第一绝缘层的部分可以覆盖虚拟结构。 形成电子器件的过程可以包括形成绝缘层的岛部，其中从顶视图看，岛部完全位于场隔离区内。

公开(公告)号：US07700499B2

公开(公告)日：2010-04-20

申请号：US12008607

申请日：2008-01-11

Applicant: Kurt H. Junker ,  Paul A. Grudowski ,  Xiang-Zheng Bo ,  Tien Ying Luo

Inventor： Kurt H. Junker ,  Paul A. Grudowski ,  Xiang-Zheng Bo ,  Tien Ying Luo

IPC: H01L21/31

CPC classification number: H01L21/823807 ,  H01L29/78 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (233) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.

Abstract translation: 提供一种制造半导体器件的方法，其包括（a）提供配备有栅极（209）和沟道区域的半导体结构，所述沟道区域与栅极相关联; （b）在半导体结构上沉积第一应力源材料的第一子层（231），所述第一应力材料含有硅 - 氮键并向半导体结构施加拉伸应力; （c）通过暴露于辐射源固化第一应激物材料; （d）在所述第一子层上沉积第二应力源材料的第二子层（233），所述第二应力材料含有硅 - 氮键并向所述半导体结构施加拉伸应力; 和（e）通过暴露于辐射源固化应力源材料的第二子层。

公开(公告)号：US07678698B2

公开(公告)日：2010-03-16

申请号：US11744581

申请日：2007-05-04

Applicant: Xiangzheng Bo ,  Tien Ying Luo ,  Kurt H. Junker ,  Paul A. Grudowski ,  Venkat R. Kolagunta

Inventor： Xiangzheng Bo ,  Tien Ying Luo ,  Kurt H. Junker ,  Paul A. Grudowski ,  Venkat R. Kolagunta

IPC: H01L21/44

CPC classification number: H01L29/7843 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/3185 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.

Abstract translation: 半导体器件具有至少两个用UV辐射固化的拉伸应力层。 在第一应力层之后形成第二拉伸应力层。 在一些实例中，拉伸应力层包括氮化硅和氢。 在一些实例中，第二拉伸应力层由于固化而比第一拉伸应力层具有更大的收缩率。 在一种形式中，固化后的第二张应力层比第一拉伸应力层具有更大的拉伸应力。 拉伸应力层用于改善N沟道晶体管中的载流子迁移率，从而提高晶体管性能。 在一种形式中，提供单组上覆的拉伸应力层，每层越来越厚，并且在固化之前具有越来越多的氢。 在其它实施方案中，形成多个重叠的基团，每个基团具有相似的重复深度和氢分布。

公开(公告)号：US07538002B2

公开(公告)日：2009-05-26

申请号：US11361171

申请日：2006-02-24

Applicant: Da Zhang ,  Vance H. Adams ,  Bich-Yen Nguyen ,  Paul A. Grudowski

Inventor： Da Zhang ,  Vance H. Adams ,  Bich-Yen Nguyen ,  Paul A. Grudowski

IPC: H01L21/336

CPC classification number: H01L29/7846 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78654

Abstract: A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.

Abstract translation: 半导体制造工艺包括在晶体管区域的任一侧上形成隔离结构，形成覆盖晶体管区域的栅极结构，去除源极/漏极区域以形成源极/漏极凹部，去除隔离结构的部分以形成凹入的隔离结构;以及 用诸如外延形成的半导体的源极/漏极应力源填充源/漏极凹部。 源极/漏极凹部的下表面优选比凹入的隔离结构的上表面深大约10至30nm。 填充源极/漏极凹部可以在形成凹入的隔离结构之前或之后。 然后将ILD应激源沉积在晶体管区域上，使得ILD应力源与源极/漏极结构的侧壁相邻，从而将ILD应激源耦合到源极/漏极应力源。 ILD应力器优选为压缩或拉伸氮化硅，并且源极/漏极结构优选为硅锗或硅碳。