公开(公告)号：US20120069479A1

公开(公告)日：2012-03-22

申请号：US12884588

申请日：2010-09-17

Applicant: Jian-Hsing LEE

Inventor： Jian-Hsing LEE

IPC: H02H9/04

CPC classification number: H01L27/0262

Abstract: The present invention discloses a power transistor device and a low dropout regulator (LDO) with electrostatic discharge protection. The power transistor device includes: a P-type metal oxide semiconductor (PMOS) field effect transistor (FET), having a source and a drain electrically connected to a voltage input terminal and a voltage output terminal respectively; and an electrostatic discharge protection device, electrically connected to the voltage input terminal and the voltage output terminal, for providing an electrostatic discharge path to protect the PMOSFET.

Abstract translation: 本发明公开了一种具有静电放电保护功率晶体管器件和低压差稳压器（LDO）。 功率晶体管器件包括：分别与电压输入端子和电压输出端子电连接的源极和漏极的P型金属氧化物半导体（PMOS）场效应晶体管（FET） 以及电连接到电压输入端子和电压输出端子的静电放电保护装置，用于提供静电放电路径以保护PMOSFET。

公开(公告)号：US20080233686A1

公开(公告)日：2008-09-25

申请号：US12113803

申请日：2008-05-01

Applicant: Jian-Hsing LEE ,  Deng-Shun Chang

Inventor： Jian-Hsing LEE ,  Deng-Shun Chang

IPC: H01L21/332

CPC classification number: H01L27/0277 ,  H01L27/0255

Abstract: An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of the diode and at least a portion of the NMOS device collectively form an ESD protection device.

Abstract translation: 静电放电（ESD）保护装置包括位于衬底中的二极管和位于与二极管相邻的衬底中的N型金属氧化物半导体（NMOS）器件，其中二极管和NMOS都耦合到输入器件，以及 二极管的至少一部分和NMOS器件的至少一部分共同形成ESD保护器件。

公开(公告)号：US20100289057A1

公开(公告)日：2010-11-18

申请号：US12777672

申请日：2010-05-11

Applicant: Ming-Song SHEU ,  Jian-Hsing LEE ,  Yu-Chang JONG ,  Chun-Chien TSAI

Inventor： Ming-Song SHEU ,  Jian-Hsing LEE ,  Yu-Chang JONG ,  Chun-Chien TSAI

IPC: H01L29/74 ,  H01L21/332

CPC classification number: H01L27/0251 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7835

Abstract: An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).

Abstract translation: 集成电路在衬底上包括至少一个晶体管。 第一保护环布置在至少一个晶体管周围。 第一保护环具有第一类型的掺杂剂。 第二保护环设置在第一保护环周围。 第二保护环具有第二类型掺杂剂。 第一掺杂区域邻近第一保护环设置。 第一掺杂区具有第二类掺杂剂。 第二掺杂区域邻近第二保护环设置。 第二掺杂区具有第一类掺杂剂。 第一保护环，第二保护环，第一掺杂区和第二掺杂区能够用作第一可控硅整流器（SCR），以基本上释放静电放电（ESD）。