公开(公告)号：US07385252B2

公开(公告)日：2008-06-10

申请号：US10950844

申请日：2004-09-27

申请人： Jian-Hsing Lee ,  Deng-Shun Chang

发明人： Jian-Hsing Lee ,  Deng-Shun Chang

IPC分类号： H01L23/62

CPC分类号： H01L27/0277 ,  H01L27/0255

摘要： An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of the diode and at least a portion of the NMOS device collectively form an ESD protection device.

摘要翻译： 静电放电（ESD）保护装置包括位于衬底中的二极管和位于与二极管相邻的衬底中的N型金属氧化物半导体（NMOS）器件，其中二极管和NMOS都耦合到输入器件，以及 二极管的至少一部分和NMOS器件的至少一部分共同形成ESD保护器件。

公开(公告)号：US06274909B1

公开(公告)日：2001-08-14

申请号：US09434562

申请日：1999-11-12

申请人： Kun-Zen Chang ,  Deng-Shun Chang ,  Rong-Tai Kao

发明人： Kun-Zen Chang ,  Deng-Shun Chang ,  Rong-Tai Kao

IPC分类号： H01L2972

CPC分类号： H01L27/0251 ,  Y10S438/983

摘要： In this invention a deep N-type wall is created surrounding an area that contains an ESD device, or circuit. The ESD device, or circuit, is connected to a chip pad and is first surrounded by a P+ guard ring. The P+ guard ring is then surrounded by the deep N-type wall to block excess current from an ESD event or voltage overshoot from reaching the internal circuitry. The deep N-type wall comprises an N+ diffusion within an N-well which is on top of a deep N-well. The height of the deep N-type wall is approximately 4 to 6 micrometers which provides a capability to absorb much of the current from an ESD event or voltage overshoot.

摘要翻译： 在本发明中，围绕包含ESD装置或电路的区域产生深N型壁。 ESD器件或电路连接到芯片焊盘，并且首先被P +保护环包围。 P +保护环然后被深N型墙包围，以阻止ESD事件或电压过冲的过电流到达内部电路。 深N型壁包括位于深N阱顶部的N阱内的N +扩散。 深N型壁的高度约为4至6微米，这提供了从ESD事件或电压过冲吸收大部分电流的能力。

公开(公告)号：US07485905B2

公开(公告)日：2009-02-03

申请号：US11459650

申请日：2006-07-25

申请人： Feng-Chi Hung ,  Jian-Hsing Lee ,  Hung-Lin Chen ,  Deng-Shun Chang

发明人： Feng-Chi Hung ,  Jian-Hsing Lee ,  Hung-Lin Chen ,  Deng-Shun Chang

IPC分类号： H01L29/80 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0692 ,  H01L29/7835

摘要： An electrostatic discharge protection device comprising a multi-finger gate, a first lightly doped region of a second conductivity, a first heavily doped region of the second conductivity, and a second lightly doped region of the second conductivity. The multi-finger gate comprises a plurality of fingers mutually connected in parallel over an active region of a first conductivity. The first lightly doped region of a second conductivity is disposed in the semiconductor substrate and between two of the fingers. The first heavily doped region of the second conductivity is disposed in the first lightly doped region of the second conductivity. The second lightly doped region of the second conductivity is beneath and adjoins the first lightly doped region of the second conductivity.

摘要翻译： 一种静电放电保护装置，包括多指门，具有第二导电性的第一轻掺杂区，第二导电性的第一重掺杂区和第二导电性的第二轻掺杂区。 多指门包括在第一导电性的有源区域上并联连接的多个指状物。 第二导电性的第一轻掺杂区域设置在半导体衬底中并且在两个指状物之间。 第二导电性的第一重掺杂区域设置在第二导电性的第一轻掺杂区域中。 第二导电性的第二轻掺杂区域位于第二导电性的第一轻掺杂区域的下方并与其邻接。

公开(公告)号：US07563653B2

公开(公告)日：2009-07-21

申请号：US12113803

申请日：2008-05-01

申请人： Jian-Hsing Lee ,  Deng-Shun Chang

发明人： Jian-Hsing Lee ,  Deng-Shun Chang

IPC分类号： H01L21/332

CPC分类号： H01L27/0277 ,  H01L27/0255

摘要： An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of the diode and at least a portion of the NMOS device collectively form an ESD protection device.

摘要翻译： 静电放电（ESD）保护装置包括位于衬底中的二极管和位于与二极管相邻的衬底中的N型金属氧化物半导体（NMOS）器件，其中二极管和NMOS都耦合到输入器件，以及 二极管的至少一部分和NMOS器件的至少一部分共同形成ESD保护器件。

公开(公告)号：US20080233686A1

公开(公告)日：2008-09-25

申请号：US12113803

申请日：2008-05-01

申请人： Jian-Hsing LEE ,  Deng-Shun Chang

发明人： Jian-Hsing LEE ,  Deng-Shun Chang

IPC分类号： H01L21/332

CPC分类号： H01L27/0277 ,  H01L27/0255

摘要： An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of the diode and at least a portion of the NMOS device collectively form an ESD protection device.

摘要翻译： 静电放电（ESD）保护装置包括位于衬底中的二极管和位于与二极管相邻的衬底中的N型金属氧化物半导体（NMOS）器件，其中二极管和NMOS都耦合到输入器件，以及 二极管的至少一部分和NMOS器件的至少一部分共同形成ESD保护器件。

公开(公告)号：US20080023766A1

公开(公告)日：2008-01-31

申请号：US11459650

申请日：2006-07-25

申请人： Feng-Chi Hung ,  Jian-Hsing Lee ,  Hung-Lin Chen ,  Deng-Shun Chang

发明人： Feng-Chi Hung ,  Jian-Hsing Lee ,  Hung-Lin Chen ,  Deng-Shun Chang

IPC分类号： H01L23/62

CPC分类号： H01L29/0847 ,  H01L29/0692 ,  H01L29/7835

摘要： An electrostatic discharge protection device comprising a multi-finger gate, a first lightly doped region of a second conductivity, a first heavily doped region of the second conductivity, and a second lightly doped region of the second conductivity. The multi-finger gate comprises a plurality of fingers mutually connected in parallel over an active region of a first conductivity. The first lightly doped region of a second conductivity is disposed in the semiconductor substrate and between two of the fingers. The first heavily doped region of the second conductivity is disposed in the first lightly doped region of the second conductivity. The second lightly doped region of the second conductivity is beneath and adjoins the first lightly doped region of the second conductivity.

摘要翻译： 一种静电放电保护装置，包括多指门，具有第二导电性的第一轻掺杂区，第二导电性的第一重掺杂区和第二导电性的第二轻掺杂区。 多指门包括在第一导电性的有源区域上并联连接的多个指状物。 第二导电性的第一轻掺杂区域设置在半导体衬底中并且在两个指状物之间。 第二导电性的第一重掺杂区域设置在第二导电性的第一轻掺杂区域中。 第二导电性的第二轻掺杂区域位于第二导电性的第一轻掺杂区域的下方并与其邻接。

公开(公告)号：US20060065931A1

公开(公告)日：2006-03-30

申请号：US10950844

申请日：2004-09-27

申请人： Jian-Hsing Lee ,  Deng-Shun Chang

发明人： Jian-Hsing Lee ,  Deng-Shun Chang

IPC分类号： H01L23/62

CPC分类号： H01L27/0277 ,  H01L27/0255

摘要： An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of the diode and at least a portion of the NMOS device collectively form an ESD protection device.