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    Circuit protection device
    1.
    发明授权
    Circuit protection device 有权
    电路保护装置

    公开(公告)号：US06927960B2

    公开(公告)日：2005-08-09

    申请号：US10282062

    申请日：2002-10-29

    申请人： Jian-Rong Huang ,  Liang-Pin Tai ,  Jing-Meng Liu

    发明人： Jian-Rong Huang ,  Liang-Pin Tai ,  Jing-Meng Liu

    IPC分类号： H02H5/04

    CPC分类号： H02H5/041

    摘要： A circuit protection device includes an overheat protecting circuit connected to a main circuit and capable of being activated so as to shut down the main circuit when operating temperature of the main circuit reaches a predetermined value, and a current limiting circuit connected to the main circuit for preventing current through the main circuit from exceeding a predetermined threshold value. The current limiting circuit is further connected to the overheat protecting circuit and controls activation of the overheat protecting circuit when the current through the main circuit reaches the predetermined threshold value. Therefore, erroneous operation of the circuit protection device due to a shift in component characteristics of the overheat protecting circuit attributed to limitations in fabrication can be avoided.

    摘要翻译： 电路保护装置包括：连接到主电路并且能够被激活以在主电路的工作温度达到预定值时关闭主电路的过热保护电路;以及连接到主电路的限流电路， 防止通过主电路的电流超过预定阈值。 当流过主电路的电流达到预定阈值时，电流限制电路进一步连接到过热保护电路，并控制过热保护电路的启动。 因此，可以避免由于制造中的限制而引起的过热保护电路的部件特性偏移导致的电路保护装置的错误操作。

    Single-chip common-drain JFET device and its applications
    2.
    发明授权
    Single-chip common-drain JFET device and its applications 失效

    公开(公告)号：US07838902B2

    公开(公告)日：2010-11-23

    申请号：US12385721

    申请日：2009-04-17

    申请人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

    发明人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

    IPC分类号： H01L29/74 ,  H01L31/111

    CPC分类号： H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

    摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

    Two-step ripple-free multi-phase buck converter and method thereof
    3.
    发明授权
    Two-step ripple-free multi-phase buck converter and method thereof 有权
    两级无波纹多相降压转换器及其方法

    公开(公告)号：US06839252B2

    公开(公告)日：2005-01-04

    申请号：US10442077

    申请日：2003-05-21

    申请人： Liang-Pin Tai ,  Shwu-Liang Hsieh ,  Hung-I Wang ,  Jing-Meng Liu

    发明人： Liang-Pin Tai ,  Shwu-Liang Hsieh ,  Hung-I Wang ,  Jing-Meng Liu

    IPC分类号： H02M3/158 ,  H02M7/00 ,  G05F1/40

    CPC分类号： H02M3/1584 ,  H02M2001/0029

    摘要： A two-step ripple-free multi-phase buck converter and method thereof comprises a first-stage voltage regulator to convert an input voltage to an intermediate voltage and a second-stage voltage regulator with a phase number not less than two to further convert the intermediate voltage to an output voltage by a split phase control, in which the ratio of the intermediate voltage to the output voltage is intended to the phase number such that the steady state output current of the converter approaches to be ripple-free, and hence the drivers and MOSFETs for the second-stage voltage regulator are lower cost, the efficiency of the second-stage voltage regulator is improved, and a higher slew rate current is obtained for transient driving capabilities.

    摘要翻译： 两级无纹波多相降压转换器及其方法包括将输入电压转换为中间电压的第一级电压调节器和相位数不少于2的第二级稳压器，以进一步转换 通过分相控制将中间电压输出到输出电压，其中中间电压与输出电压的比率旨在达到相位数，使得转换器的稳态输出电流接近无波纹，因此 第二级稳压器的驱动器和MOSFET的成本较低，二级稳压器的效率得到提高，瞬态驱动能力可获得更高的转换速率电流。

    Apparatus and method for balancing channel currents in a multi-phase DC-to-DC converter
    4.
    发明授权
    Apparatus and method for balancing channel currents in a multi-phase DC-to-DC converter 有权
    用于平衡多相DC-DC转换器中的通道电流的装置和方法

    公开(公告)号：US06414470B1

    公开(公告)日：2002-07-02

    申请号：US10051136

    申请日：2002-01-22

    申请人： Jing-Meng Liu ,  Liang-Pin Tai ,  Hung-I Wang

    发明人： Jing-Meng Liu ,  Liang-Pin Tai ,  Hung-I Wang

    IPC分类号： G05F140

    CPC分类号： H02M3/1584 ,  H02J1/102

    摘要： An apparatus and method for current balance in a multi-phase DC-to-DC converter with a converter output voltage and a plurality of channel currents employs for each channel a multi-input pulse width modulator or an ordinary pulse width modulator in conjunction with a multi-input comparator to produce a respective PWM signal to regulate the corresponding channel current. In addition to the comparison of the converter output voltage with a reference signal to produce an error signal, the apparatus and method compares the error signal with a ramp signal and the corresponding channel current with each of the other channel currents with the multi-input pulse width modulator. Alternatively, a ramp signal is compared by the ordinary pulse width modulator with a signal derived from the multi-input comparator which subtracts the corresponding channel current from each other channel current and sums the error signal.

    摘要翻译： 具有转换器输出电压和多个通道电流的多相DC-DC转换器中的电流平衡的装置和方法为每个通道使用多输入脉宽调制器或普通脉冲宽度调制器 多输入比较器产生相应的PWM信号来调节相应的通道电流。 除了将转换器输出电压与参考信号进行比较以产生误差信号之外，装置和方法还将误差信号与斜波信号和相应的通道电流与多输入脉冲中的每一个通道电流进行比较 宽度调制器 或者，通过普通脉冲宽度调制器将斜坡信号与从多输入比较器导出的信号进行比较，该信号从彼此的通道电流中减去对应的通道电流，并对误差信号求和。

    Single-chip common-drain JFET device and its applications
    5.
    发明授权
    Single-chip common-drain JFET device and its applications 失效
    单片共漏极JFET器件及其应用

    公开(公告)号：US07838900B2

    公开(公告)日：2010-11-23

    申请号：US12385718

    申请日：2009-04-17

    申请人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

    发明人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

    IPC分类号： H01L29/74 ,  H01L31/111

    CPC分类号： H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

    摘要： A single-chip common-drain JFET device comprises a Drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

    摘要翻译： 单芯片公共漏极JFET器件包括漏极，两个栅极和两个源极，使得与其形成两个公共漏极JFET。 由于在单个芯片内合并的两个JFET，其间不需要引线接合连接，因此没有由接合线引起的寄生电感和电阻，因此提高性能并降低封装成本。 单片式公共漏极JFET器件可以应用于降压转换器，升压转换器，反相转换器，开关和两级DC-DC转换器，以提高其性能和效率。 还提供了用于电流感测或比例电流产生的替代单芯片公共漏极JFET器件。

    Single-chip common-drain JFET device and its applications
    6.
    发明申请
    Single-chip common-drain JFET device and its applications 有权

    公开(公告)号：US20090201079A1

    公开(公告)日：2009-08-13

    申请号：US12385720

    申请日：2009-04-17

    申请人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

    发明人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

    IPC分类号： G05F3/02

    CPC分类号： H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

    摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

    Single-chip common-drain JFET device and its applications
    8.
    发明申请
    Single-chip common-drain JFET device and its applications 失效

    公开(公告)号：US20090237062A1

    公开(公告)日：2009-09-24

    申请号：US12385721

    申请日：2009-04-17

    申请人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

    发明人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

    IPC分类号： G05F3/24

    CPC分类号： H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

    摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

    Single-chip common-drain JFET device and its applications
    9.
    发明申请
    Single-chip common-drain JFET device and its applications 失效

    公开(公告)号：US20090206922A1

    公开(公告)日：2009-08-20

    申请号：US12385718

    申请日：2009-04-17

    申请人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

    发明人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

    IPC分类号： G05F3/02

    CPC分类号： H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

    摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

    Single-chip common-drain JFET device and its applications
    10.
    发明申请
    Single-chip common-drain JFET device and its applications 失效

    公开(公告)号：US20090201078A1

    公开(公告)日：2009-08-13

    申请号：US12385719

    申请日：2009-04-17

    申请人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

    发明人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

    IPC分类号： G05F3/02

    CPC分类号： H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

    摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.