公开(公告)号：US08115209B2

公开(公告)日：2012-02-14

申请号：US13026453

申请日：2011-02-14

申请人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

发明人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

IPC分类号： H01L29/04 ,  H01L29/15 ,  H01L31/036 ,  H01L29/10 ,  H01L31/0376 ,  H01L31/20 ,  H01L29/76 ,  H01L31/112 ,  H01L27/108 ,  H01L29/12 ,  H01L31/062 ,  H01L31/113 ,  H01L31/00

CPC分类号： H01L29/78645 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/78621

摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

摘要翻译： 公开了液晶显示器的薄膜晶体管的双栅极布局，以减轻暗电流泄漏。 该布局包括：（1）具有从顶部形成的L形或蛇形的衬底上的多晶硅，其具有重掺杂源极区，第一轻掺杂区，第一栅极沟道，第二轻掺杂区域， 第二栅极沟道，第三轻掺杂区和重掺杂漏极区; （2）形成在多晶硅层和基板上的栅极氧化层，（3）然后在栅极氧化物层上形成栅极金属层，栅极氧化物层具有扫描线和具有L形或I形的延伸部分。 栅极金属与多晶硅层相交，限定了前述栅极沟道。 在栅极通道中，沿着信号线至少有一个通过源极接触连接到源极区域。

公开(公告)号：US07910933B2

公开(公告)日：2011-03-22

申请号：US12469298

申请日：2009-05-20

申请人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

发明人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

IPC分类号： H01L29/04 ,  H01L29/15 ,  H01L31/036 ,  H01L29/10 ,  H01L31/0376 ,  H01L31/20 ,  H01L29/76 ,  H01L31/112 ,  H01L27/108 ,  H01L29/12 ,  H01L31/062 ,  H01L31/113 ,  H01L31/00

CPC分类号： H01L29/78645 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/78621

摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

摘要翻译： 公开了液晶显示器的薄膜晶体管的双栅极布局，以减轻暗电流泄漏。 该布局包括：（1）具有从顶部形成的L形或蛇形的衬底上的多晶硅，其具有重掺杂源极区，第一轻掺杂区，第一栅极沟道，第二轻掺杂区域， 第二栅极沟道，第三轻掺杂区和重掺杂漏极区; （2）形成在多晶硅层和基板上的栅极氧化层，（3）然后在栅极氧化物层上形成栅极金属层，栅极氧化物层具有扫描线和具有L形或I形的延伸部分。 栅极金属与多晶硅层相交，限定了前述栅极沟道。 在栅极通道中，沿着信号线至少有一个通过源极接触连接到源极区域。

公开(公告)号：US07858988B2

公开(公告)日：2010-12-28

申请号：US12469280

申请日：2009-05-20

申请人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

发明人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

IPC分类号： H01L27/14 ,  H01L29/04 ,  H01L29/18 ,  H01L31/036 ,  H01L27/088

CPC分类号： H01L29/78645 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/78621

摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

摘要翻译： 公开了液晶显示器的薄膜晶体管的双栅极布局，以减轻暗电流泄漏。 布局包括（1）在基板上具有从顶视图形成的L形或蛇形的多晶硅，其具有重掺杂的源极区，第一轻掺杂区，第一栅极沟道，第二轻掺杂区， 第二栅极沟道，第三轻掺杂区和重掺杂漏极区; （2）形成在多晶硅层和基板上的栅极氧化层，（3）然后在栅极氧化物层上形成栅极金属层，栅极氧化物层具有扫描线和具有L形或I形的延伸部分。 栅极金属与多晶硅层相交，限定了前述栅极沟道。 在栅极通道中，沿着信号线至少有一个通过源极接触连接到源极区域。

公开(公告)号：US07550770B2

公开(公告)日：2009-06-23

申请号：US11211606

申请日：2005-08-26

申请人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

发明人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

IPC分类号： H01L27/14 ,  H01L29/04 ,  H01L29/18 ,  H01L31/036 ,  H01L27/088

CPC分类号： H01L29/78645 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/78621

摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

摘要翻译： 公开了液晶显示器的薄膜晶体管的双栅极布局，以减轻暗电流泄漏。 布局包括（1）在基板上具有从顶视图形成的L形或蛇形的多晶硅，其具有重掺杂的源极区，第一轻掺杂区，第一栅极沟道，第二轻掺杂区， 第二栅极沟道，第三轻掺杂区和重掺杂漏极区; （2）形成在多晶硅层和基板上的栅极氧化层，（3）然后在栅极氧化物层上形成栅极金属层，栅极氧化物层具有扫描线和具有L形或I形的延伸部分。 栅极金属与多晶硅层相交，限定了前述栅极沟道。 在栅极通道中，沿着信号线至少有一个通过源极接触连接到源极区域。

公开(公告)号：US07084843B2

公开(公告)日：2006-08-01

申请号：US10604629

申请日：2003-08-06

申请人： Jian-Shen Yu ,  Wein-Town Sun

发明人： Jian-Shen Yu ,  Wein-Town Sun

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G2300/0408

摘要： An integrated driver device frame of a liquid crystal display panel is provided. The integrated driver device frame comprises a plurality of driver units, a plurality of driver lines and a plurality of output terminals. Each output terminal is coupled to a corresponding pixel element respectively. In the integrated driver device frame of the invention, the plurality of driver units is arranged with two staggered rows, in order that the driver unit width is larger than the interval of every neighboring two output terminals and is less than two times of the interval. Accordingly, the interval of two neighboring output terminals can be equal to the pixel pitch and the dot-per-inch resolution of the LCD panel can be enhanced.

摘要翻译： 提供了一种液晶显示面板的集成驱动器装置框架。 集成驱动器装置框架包括多个驱动器单元，多个驱动器线和多个输出端子。 每个输出端分别耦合到相应的像素元件。 在本发明的集成驱动器装置框架中，多个驱动器单元布置有两个交错列，以便驱动器单元宽度大于每个相邻两个输出端子的间隔，并且小于间隔的两倍。 因此，两个相邻输出端子的间隔可以等于像素间距，并且可以提高LCD面板的每英寸点数分辨率。

公开(公告)号：US20110133200A1

公开(公告)日：2011-06-09

申请号：US13026453

申请日：2011-02-14

申请人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

发明人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

IPC分类号： H01L29/04

CPC分类号： H01L29/78645 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/78621

摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

摘要翻译： 公开了液晶显示器的薄膜晶体管的双栅极布局，以减轻暗电流泄漏。 该布局包括：（1）具有从顶部形成的L形或蛇形的衬底上的多晶硅，其具有重掺杂源极区，第一轻掺杂区，第一栅极沟道，第二轻掺杂区域， 第二栅极沟道，第三轻掺杂区和重掺杂漏极区; （2）形成在多晶硅层和基板上的栅极氧化层，（3）然后在栅极氧化物层上形成栅极金属层，栅极氧化物层具有扫描线和具有L形或I形的延伸部分。 栅极金属与多晶硅层相交，限定了前述栅极沟道。 在栅极通道中，沿着信号线至少有一个通过源极接触连接到源极区域。

公开(公告)号：US20090236606A1

公开(公告)日：2009-09-24

申请号：US12469280

申请日：2009-05-20

申请人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

发明人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

IPC分类号： H01L29/786 ,  H01L33/00

CPC分类号： H01L29/78645 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/78621

摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

摘要翻译： 公开了液晶显示器的薄膜晶体管的双栅极布局，以减轻暗电流泄漏。 布局包括（1）在基板上具有从顶视图形成的L形或蛇形的多晶硅，其具有重掺杂的源极区，第一轻掺杂区，第一栅极沟道，第二轻掺杂区， 第二栅极沟道，第三轻掺杂区和重掺杂漏极区; （2）形成在多晶硅层和基板上的栅极氧化层，（3）然后在具有扫描线的栅极氧化物层和具有L形或I形的延伸部分的栅极金属层上形成栅极金属层。 栅极金属与多晶硅层相交，限定了前述栅极沟道。 在栅极通道中，沿着信号线至少有一个通过源极接触连接到源极区域。

公开(公告)号：US06936848B2

公开(公告)日：2005-08-30

申请号：US10624479

申请日：2003-07-23

申请人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

发明人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

IPC分类号： H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/15 ,  H01L21/00 ,  G02F11/333

CPC分类号： H01L29/78645 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/78621

摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

公开(公告)号：US08288774B2

公开(公告)日：2012-10-16

申请号：US13348715

申请日：2012-01-12

申请人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

发明人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

IPC分类号： H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L29/04 ,  H01L31/0376 ,  H01L31/20 ,  H01L29/15 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07 ,  H01L31/108

CPC分类号： H01L29/78645 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/78621

摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a shaped of L- or of snake from top-view, having a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the poly-Si layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the poly-Si layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line through a source contact.

摘要翻译： 公开了液晶显示器的薄膜晶体管的双栅极布局，以减轻暗电流泄漏。 该布局包括（1）在基底上的多晶硅，其具有顶部具有L-或蛇形的形状，具有重掺杂的源极区，第一轻掺杂区，第一栅极通道，第二轻掺杂区， 第二栅极沟道，第三轻掺杂区和重掺杂漏极区; （2）形成在多晶硅层和基板上的栅极氧化层，（3）然后在具有扫描线的栅极氧化物层上形成栅极金属层，并且具有L形或I形的延伸部分 。 栅极金属与多晶硅层相交，限定了前述栅极沟道。 在栅极通道中，至少有一个沿着信号线通过源极接触。

公开(公告)号：US20090230403A1

公开(公告)日：2009-09-17

申请号：US12469298

申请日：2009-05-20

申请人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

发明人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

IPC分类号： H01L29/786 ,  H01L33/00

CPC分类号： H01L29/78645 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/78621

摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.