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    Cache line pre-load and pre-own based on cache coherence speculation
    1.
    发明授权
    Cache line pre-load and pre-own based on cache coherence speculation 有权
    缓存线预加载和基于缓存一致性推测的预先拥有

    公开(公告)号：US06725341B1

    公开(公告)日：2004-04-20

    申请号：US09605239

    申请日：2000-06-28

    申请人： Jih-Kwon Peir ,  Steve Y. Zhang ,  Scott H. Robinson ,  Konrad Lai ,  Wen-Hann Wang

    发明人： Jih-Kwon Peir ,  Steve Y. Zhang ,  Scott H. Robinson ,  Konrad Lai ,  Wen-Hann Wang

    IPC分类号： G06F1200

    CPC分类号： G06F12/0831

    摘要： The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.

    摘要翻译： 本发明提供一种缓存管理系统，其包括在各种实施例中预先加载和预先拥有的功能，以增强共享存储器分布式高速缓存多处理器计算机系统中的高速缓存效率。 本发明的一些实施例包括无效历史表，用于记录通过脏或无效无效而无效的高速缓存行的行地址，并且其被使用，使得记录在无效历史表中的无效高速缓存行通过监视高速缓存的总线被重新加载到高速缓存中 记录在无效历史表中的高速缓存行的行地址。 在一些另外的实施例中，与每个L2高速缓存条目相关联的回写位在检测到另一个处理器中的同一行的命中时或者当另一个处理器的高速缓存中的同一行无效时记录，并且系统广播回写从 所选择的本地缓存只有当正在写回的行具有已设置的回写位时。

    Cache line pre-load and pre-own based on cache coherence speculation
    2.
    发明授权
    Cache line pre-load and pre-own based on cache coherence speculation 失效
    缓存线预加载和基于缓存一致性推测的预先拥有

    公开(公告)号：US07076613B2

    公开(公告)日：2006-07-11

    申请号：US10761995

    申请日：2004-01-21

    申请人： Jih-Kwon Peir ,  Steve Y. Zhang ,  Scott H. Robinson ,  Konrad Lai ,  Wen-Hann Wang

    发明人： Jih-Kwon Peir ,  Steve Y. Zhang ,  Scott H. Robinson ,  Konrad Lai ,  Wen-Hann Wang

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0831

    摘要： The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.

    摘要翻译： 本发明提供一种缓存管理系统，其包括在各种实施例中预先加载和预先拥有的功能，以增强共享存储器分布式高速缓存多处理器计算机系统中的高速缓存效率。 本发明的一些实施例包括无效历史表，用于记录通过脏或无效无效而无效的高速缓存行的行地址，并且其被使用，使得记录在无效历史表中的无效高速缓存行通过监视高速缓存的总线被重新加载到高速缓存中 记录在无效历史表中的高速缓存行的行地址。 在一些另外的实施例中，与每个L2高速缓存条目相关联的回写位在检测到另一个处理器中的同一行的命中时或者当另一个处理器的高速缓存中的同一行无效时记录，并且系统广播回写从 所选择的本地缓存只有当正在写回的行具有已设置的回写位时。

    Processsor integral technologies for BIOS flash attack protection and notification
    6.
    发明授权
    Processsor integral technologies for BIOS flash attack protection and notification 有权
    用于BIOS闪存攻击保护和通知的进程集成技术

    公开(公告)号：US09015455B2

    公开(公告)日：2015-04-21

    申请号：US13178338

    申请日：2011-07-07

    申请人： James P. Held ,  Scott H. Robinson ,  Vincent J. Zimmer

    发明人： James P. Held ,  Scott H. Robinson ,  Vincent J. Zimmer

    IPC分类号： G06F9/00 ,  G06F21/57 ,  G06F9/44

    CPC分类号： G06F21/575 ,  G06F9/4401 ,  G06F21/64

    摘要： A system and method for BIOS flash attack protection and notification. A processor initialization module, including initialization firmware verification module may be configured to execute first in response to a power on and/or reset and to verify initialization firmware stored in non-volatile memory in a processor package. The initialization firmware is configured to verify the BIOS. If the verification of the initialization firmware and/or the BIOS fails, the system is configured to select at least one of a plurality of responses including, but not limited to, preventing the BIOS from executing, initiating recovery, reporting the verification failure, halting, shutting down and/or allowing the BIOS to execute and an operating system (OS) to boot in a limited functionality mode.

    摘要翻译： 用于BIOS闪存防护和通知的系统和方法。 包括初始化固件验证模块的处理器初始化模块可以被配置为响应于电源接通和/或复位而首先执行并且验证处理器封装中存储在非易失性存储器中的初始化固件。 初始化固件配置为验证BIOS。 如果初始化固件和/或BIOS的验证失败，则系统被配置为选择多个响应中的至少一个，包括但不限于防止BIOS执行，启动恢复，报告验证失败，停止 ，关闭和/或允许BIOS执行，以及操作系统（OS）以有限的功能模式进行引导。

    Method and apparatus for differential, bandwidth-efficient and storage-efficient backups
    7.
    发明授权
    Method and apparatus for differential, bandwidth-efficient and storage-efficient backups 有权
    差分，带宽高效和高效存储备份的方法和设备

    公开(公告)号：US07257257B2

    公开(公告)日：2007-08-14

    申请号：US10644445

    申请日：2003-08-19

    申请人： Andrew V. Anderson ,  Steven M. Bennett ,  Scott H. Robinson

    发明人： Andrew V. Anderson ,  Steven M. Bennett ,  Scott H. Robinson

    IPC分类号： G06K9/00

    CPC分类号： G06F11/1464 ,  G06F11/1451

    摘要： A process is introduced that determines contour requirements from many factors. Based on the contour requirements, the process either generates at least one content-derived signature contour from either many content identifiers or at least one content-derived signature contour, or generates at least one optimized content-derived signature contour from contour-related data and either at least one content-derived signature contour or a derivation from at least one content-derived signature contour.

    摘要翻译： 引入了一个从许多因素确定轮廓要求的过程。 基于轮廓要求，该过程或者从许多内容标识符或至少一个内容导出的签名轮廓生成至少一个内容导出签名轮廓，或者从轮廓相关数据生成至少一个优化的内容导出签名轮廓，以及 至少一个内容导出的签名轮廓或从至少一个内容导出的签名轮廓的派生。

    Providing Silicon Integrated Code For A System
    8.
    发明申请
    Providing Silicon Integrated Code For A System 审中-公开
    为系统提供硅集成代码

    公开(公告)号：US20140013095A1

    公开(公告)日：2014-01-09

    申请号：US13935767

    申请日：2013-07-05

    申请人： Vincent J. Zimmer ,  Bin Xing ,  Scott H. Robinson

    发明人： Vincent J. Zimmer ,  Bin Xing ,  Scott H. Robinson

    IPC分类号： G06F9/44

    CPC分类号： G06F9/4401 ,  G06F11/073 ,  G06F11/076 ,  G06F11/1092 ,  G06F21/14 ,  G06F21/572 ,  G06F21/575

    摘要： In one embodiment, a semiconductor integrated code (SIC) may be provided in a binary format by a processor manufacturer. This SIC may include platform independent code of the processor manufacturer. Such code may include embedded processor logic to initialize the processor and at least one link that couples the processor to a memory, and embedded memory logic to initialize the memory. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，半导体集成代码（SIC）可由处理器制造商以二进制格式提供。 该SIC可以包括处理器制造商的平台无关代码。 这样的代码可以包括用于初始化处理器的嵌入式处理器逻辑和将处理器耦合到存储器的至少一个链路以及嵌入式存储器逻辑以初始化存储器。 描述和要求保护其他实施例。

    ACCESSING PRIVATE DATA ABOUT THE STATE OF A DATA PROCESSING MACHINE FROM STORAGE THAT IS PUBLICLY ACCESSIBLE
    9.
    发明申请
    ACCESSING PRIVATE DATA ABOUT THE STATE OF A DATA PROCESSING MACHINE FROM STORAGE THAT IS PUBLICLY ACCESSIBLE 审中-公开
    访问私人数据关于数据处理机器的状态，从存储可以访问的存储

    公开(公告)号：US20130275772A1

    公开(公告)日：2013-10-17

    申请号：US13836863

    申请日：2013-03-15

    申请人： Scott H. Robinson ,  Gustavo P. Espinosa ,  Steven M. Bennett

    发明人： Scott H. Robinson ,  Gustavo P. Espinosa ,  Steven M. Bennett

    IPC分类号： G06F12/14

    CPC分类号： G06F12/1408 ,  G06F21/71 ,  G06F21/78

    摘要： According to an embodiment of the invention, a method for operating a data processing machine is described in which data about a state of the machine is written to a location in storage. The location is one that is accessible to software that may be written for the machine. The state data as written is encoded. This state data may be recovered from the storage according to a decoding process. Other embodiments are also described and claimed.

    摘要翻译： 根据本发明的实施例，描述了一种用于操作数据处理机器的方法，其中关于机器状态的数据被写入存储器中的位置。 该位置是可以为机器编写的软件可访问的位置。 写入的状态数据被编码。 该状态数据可以根据解码处理从存储器恢复。 还描述和要求保护其他实施例。

    Method, apparatus and system for enhancing the usability of virtual machines
    10.
    发明授权
    Method, apparatus and system for enhancing the usability of virtual machines 失效
    提高虚拟机可用性的方法，装置和系统

    公开(公告)号：US08479193B2

    公开(公告)日：2013-07-02

    申请号：US11016654

    申请日：2004-12-17

    申请人： Scott H. Robinson ,  Vijay Tewari ,  Robert C. Knauerhase

    发明人： Scott H. Robinson ,  Vijay Tewari ,  Robert C. Knauerhase

    IPC分类号： G06F9/455

    CPC分类号： G06F21/55 ,  G06F9/45533

    摘要： A method, apparatus and system for improving usability of virtual machines is described. A console module on a VM host may continuously monitor incoming data (e.g., files and/or attachments) and make automatic determinations regarding how and/or whether to intercept, route, redirect and/or deliver the data (e.g., where to store files, when and/or whether to deliver the files, execute the files, etc.). Additionally, in one embodiment, a unification console may be provided to enhance the usability of the VM host. The unification console enables the user to view the VM host via a unified desktop interface while handling the underlying switching and/or interactions between VMs.

    摘要翻译： 描述了一种用于提高虚拟机的可用性的方法，装置和系统。 VM主机上的控制台模块可以连续监视传入的数据（例如，文件和/或附件），并自动确定是如何和/或是否拦截，路由，重定向和/或传送数据（例如，哪里存储文件 ，何时和/或是否传送文件，执行文件等）。 此外，在一个实施例中，可以提供统一控制台以增强VM主机的可用性。 统一控制台使用户能够通过统一的桌面界面来查看VM主机，同时处理虚拟机之间的底层交换和/或交互。