公开(公告)号：US20110289295A1

公开(公告)日：2011-11-24

申请号：US13147534

申请日：2010-04-02

申请人： Shigang Chen ,  Jih-Kwon Peir ,  Myungkeun Yoon ,  Tao Li

发明人： Shigang Chen ,  Jih-Kwon Peir ,  Myungkeun Yoon ,  Tao Li

IPC分类号： G06F12/02

CPC分类号： H04L43/022 ,  H04L41/142 ,  H04L43/026 ,  H04L49/901

摘要： A data structure is provided for storing network contact information based on an array of physical memory locations. Virtual vectors are constructed for each source, wherein each element in each virtual vector is assigned to a corresponding physical memory location within the array. The physical memory locations are shared between the virtual vectors uniformly at random so that the noise introduced by sharing can be predicted and removed. A method for storing network contact information is also provided in which a hash function is performed using the address of a source host to find a virtual vector for holding information about the source host. A second hash function is performed using the address of a destination host to find a virtual memory location, within the virtual vector, for holding information about the destination host. Finally, information is stored at a physical memory location assigned to the virtual memory location. Estimation range enhancement is further provided by performing multiple estimations with different sampling probabilities and selecting a best estimation based on a maximum likelihood method.

摘要翻译： 提供了一种数据结构，用于基于物理存储器位置的阵列来存储网络联系信息。 为每个源构建虚拟向量，其中每个虚拟向量中的每个元素被分配给阵列内的对应物理存储器位置。 物理存储器位置在虚拟向量之间被随机均匀地共享，使得可以预测和去除通过共享引入的噪声。 还提供了一种用于存储网络联系信息的方法，其中使用源主机的地址执行散列函数，以找到用于保存关于源主机的信息的虚拟向量。 使用目的地主机的地址来执行第二散列函数，以在虚拟向量内找到用于保存关于目的地主机的信息的虚拟存储器位置。 最后，信息被存储在分配给虚拟存储器位置的物理存储器位置。 通过执行具有不同采样概率的多个估计并基于最大似然法选择最佳估计来进一步提供估计范围增强。

公开(公告)号：US06711662B2

公开(公告)日：2004-03-23

申请号：US09823251

申请日：2001-03-29

申请人： Jih-Kwon Peir ,  Konrad Lai

发明人： Jih-Kwon Peir ,  Konrad Lai

IPC分类号： G06F1200

CPC分类号： G06F12/0817 ,  G06F2212/507

摘要： A shared-memory system includes processing modules communicating with each other through a network. Each of the processing modules includes a processor, a cache, and a memory unit that is locally accessible by the processor and remotely accessible via the network by all other processors. A home directory records states and locations of data blocks in the memory unit. A prediction facility that contains reference history information of the data blocks predicts a next requester of a number of the data blocks that have been referenced recently. The next requester is informed by the prediction facility of the current owner of the data block. As a result, the next requester can issue a request to the current owner directly without an additional hop through the home directory.

摘要翻译： 共享存储器系统包括通过网络彼此通信的处理模块。 每个处理模块包括处理器，高速缓存和存储器单元，其可由处理器本地访问并且可被所有其他处理器经由网络远程访问。 主目录记录存储器单元中的数据块的状态和位置。 包含数据块的参考历史信息的预测设备预测最近已被引用的数个数据块的下一个请求者。 下一个请求者由数据块的当前所有者的预测设备通知。 因此，下一个请求者可以直接向当前所有者发出请求，而无需通过主目录进行额外的跳转。

公开(公告)号：US5148538A

公开(公告)日：1992-09-15

申请号：US424496

申请日：1989-10-20

申请人： Joseph O. Celtruda ,  Kein A. Hua ,  Anderson H. Hunt ,  Lishing Liu ,  Jih-Kwon Peir ,  David R. Pruett ,  Joseph L. Temple, III

发明人： Joseph O. Celtruda ,  Kein A. Hua ,  Anderson H. Hunt ,  Lishing Liu ,  Jih-Kwon Peir ,  David R. Pruett ,  Joseph L. Temple, III

IPC分类号： G06F12/08 ,  G06F9/38 ,  G06F12/10 ,  G06F12/12

CPC分类号： G06F12/1054 ,  G06F9/383 ,  G06F9/3832 ,  G06F2212/654

摘要： This invention implements a cache access system that shortens the address generation machine cycle of a digital computer, while simultaneously avoiding the synonym problem of logical addressing. The invention is based on the concept of predicting what the real address used in the cache memory will be, independent of the generation of the logical address. The prediction involves recalling the last real address used to access the cache memory for a particular instruction, and then using that real address to access the cache memory. Incorrect guesses are corrected and kept to a minimum through monitoring the history of instructions and real addresses called for in the computer. This allows the cache memory to retrieve the information faster than waiting for the virtual address to be generated and then translating the virtual address into a real address. The address generation machine cycle is faster because the delays associated with the adder of the virtual address generation means and the translation buffer are bypassed.

公开(公告)号：US06725341B1

公开(公告)日：2004-04-20

申请号：US09605239

申请日：2000-06-28

申请人： Jih-Kwon Peir ,  Steve Y. Zhang ,  Scott H. Robinson ,  Konrad Lai ,  Wen-Hann Wang

发明人： Jih-Kwon Peir ,  Steve Y. Zhang ,  Scott H. Robinson ,  Konrad Lai ,  Wen-Hann Wang

IPC分类号： G06F1200

CPC分类号： G06F12/0831

摘要： The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.

摘要翻译： 本发明提供一种缓存管理系统，其包括在各种实施例中预先加载和预先拥有的功能，以增强共享存储器分布式高速缓存多处理器计算机系统中的高速缓存效率。 本发明的一些实施例包括无效历史表，用于记录通过脏或无效无效而无效的高速缓存行的行地址，并且其被使用，使得记录在无效历史表中的无效高速缓存行通过监视高速缓存的总线被重新加载到高速缓存中 记录在无效历史表中的高速缓存行的行地址。 在一些另外的实施例中，与每个L2高速缓存条目相关联的回写位在检测到另一个处理器中的同一行的命中时或者当另一个处理器的高速缓存中的同一行无效时记录，并且系统广播回写从 所选择的本地缓存只有当正在写回的行具有已设置的回写位时。

公开(公告)号：US08842690B2

公开(公告)日：2014-09-23

申请号：US13147534

申请日：2010-04-02

申请人： Shigang Chen ,  Jih-Kwon Peir ,  Myungkeun Yoon ,  Tao Li

发明人： Shigang Chen ,  Jih-Kwon Peir ,  Myungkeun Yoon ,  Tao Li

IPC分类号： H04N1/21 ,  H04L12/26 ,  H04L12/879 ,  H04L12/24

CPC分类号： H04L43/022 ,  H04L41/142 ,  H04L43/026 ,  H04L49/901

摘要： A data structure is provided for storing network contact information based on an array of physical memory locations. Virtual vectors are constructed for each source, wherein each element in each virtual vector is assigned to a corresponding physical memory location within the array. The physical memory locations are shared between the virtual vectors uniformly at random so that the noise introduced by sharing can be predicted and removed. A method for storing network contact information is also provided in which a hash function is performed using the address of a source host to find a virtual vector for holding information about the source host. A second hash function is performed using the address of a destination host to find a virtual memory location, within the virtual vector, for holding information about the destination host. Finally, information is stored at a physical memory location assigned to the virtual memory location. Estimation range enhancement is further provided by performing multiple estimations with different sampling probabilities and selecting a best estimation based on a maximum likelihood method.

摘要翻译： 提供了一种数据结构，用于基于物理存储器位置的阵列来存储网络联系信息。 为每个源构建虚拟向量，其中每个虚拟向量中的每个元素被分配给阵列内的对应物理存储器位置。 物理存储器位置在虚拟向量之间被随机均匀地共享，使得可以预测和去除通过共享引入的噪声。 还提供了一种用于存储网络联系信息的方法，其中使用源主机的地址执行散列函数，以找到用于保存关于源主机的信息的虚拟向量。 使用目的地主机的地址来执行第二散列函数，以在虚拟向量内找到用于保存关于目的地主机的信息的虚拟存储器位置。 最后，信息被存储在分配给虚拟存储器位置的物理存储器位置。 通过执行具有不同采样概率的多个估计并基于最大似然法选择最佳估计来进一步提供估计范围增强。

公开(公告)号：US07076613B2

公开(公告)日：2006-07-11

申请号：US10761995

申请日：2004-01-21

申请人： Jih-Kwon Peir ,  Steve Y. Zhang ,  Scott H. Robinson ,  Konrad Lai ,  Wen-Hann Wang

发明人： Jih-Kwon Peir ,  Steve Y. Zhang ,  Scott H. Robinson ,  Konrad Lai ,  Wen-Hann Wang

IPC分类号： G06F12/00

CPC分类号： G06F12/0831

摘要： The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.

摘要翻译： 本发明提供一种缓存管理系统，其包括在各种实施例中预先加载和预先拥有的功能，以增强共享存储器分布式高速缓存多处理器计算机系统中的高速缓存效率。 本发明的一些实施例包括无效历史表，用于记录通过脏或无效无效而无效的高速缓存行的行地址，并且其被使用，使得记录在无效历史表中的无效高速缓存行通过监视高速缓存的总线被重新加载到高速缓存中 记录在无效历史表中的高速缓存行的行地址。 在一些另外的实施例中，与每个L2高速缓存条目相关联的回写位在检测到另一个处理器中的同一行的命中时或者当另一个处理器的高速缓存中的同一行无效时记录，并且系统广播回写从 所选择的本地缓存只有当正在写回的行具有已设置的回写位时。

公开(公告)号：US6128755A

公开(公告)日：2000-10-03

申请号：US295493

申请日：1994-08-25

申请人： Stephen Edward Bello ,  Kien Anh Hua ,  Jih-Kwon Peir

发明人： Stephen Edward Bello ,  Kien Anh Hua ,  Jih-Kwon Peir

IPC分类号： G06F11/18 ,  G06F15/16 ,  G06F15/177 ,  G01R31/28

CPC分类号： G06F11/182 ,  G06F11/1687 ,  G06F11/1691 ,  G06F2201/83

摘要： A multiprocessor computer system and associated method having processing error detection capability is disclosed for error-free processing of an instruction set. The instruction set is replicated and processed substantially in parallel through a plurality of processing nodes of the computer system. Each processing node collects a compressed hardware signature commensurate with and derived from the execution of the instruction set. Subsequent instruction set processing, the collected hardware signatures from each processing node are compared and the presence or absence of a processing error is determined with reference to a predetermined voting scheme. Processing of the instruction sets through the plurality of processing nodes is typically asynchronous with synchronization occurring subsequent each processor's execution of the instruction set, such that each processor can be driven by an independent clock.

摘要翻译： 公开了一种具有处理错误检测能力的多处理器计算机系统和相关方法，用于无指令处理指令集。 指令集通过计算机系统的多个处理节点基本并行地进行复制和处理。 每个处理节点收集与指令集的执行相称并从其执行的压缩硬件签名。 随后的指令集处理，比较来自每个处理节点的所收集的硬件签名，参考预定的投票方案来确定是否存在处理错误。 通过多个处理节点对指令集的处理通常与在每个处理器执行指令集之后发生的同步异步，使得每个处理器可以由独立时钟驱动。