利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

34 条记录 (耗时 0.023 秒)

    Semiconductor device and lateral diffused metal-oxide-semiconductor transistor
    1.
    发明授权
    Semiconductor device and lateral diffused metal-oxide-semiconductor transistor 有权
    半导体器件和横向扩散金属氧化物半导体晶体管

    公开(公告)号：US08093630B2

    公开(公告)日：2012-01-10

    申请号：US12477054

    申请日：2009-06-02

    申请人： Jimmy Lin ,  Shang-Hui Tu ,  Ming-Horng Hsiao

    发明人： Jimmy Lin ,  Shang-Hui Tu ,  Ming-Horng Hsiao

    IPC分类号： H01L27/088

    CPC分类号： H01L29/7393 ,  H01L27/0262 ,  H01L29/0696 ,  H01L29/7436 ,  H01L29/87

    摘要： The invention provides a semiconductor device and a lateral diffused metal-oxide-semiconductor transistor. The semiconductor device includes a substrate having a first conductive type. A gate is disposed on the substrate. A source doped region is formed in the substrate, neighboring with a first side of the gate, wherein the source doped region has a second conductive type different from the first conductive type. A drain doped region is formed in the substrate, neighboring with a second side opposite to the first side of the gate. The drain doped region is constructed by a plurality of first doped regions with the first conductive type and a plurality of second doped regions with the second conductive type, wherein the first doped regions and the second doped regions are alternatively arranged.

    摘要翻译： 本发明提供一种半导体器件和横向漫射金属氧化物半导体晶体管。 半导体器件包括具有第一导电类型的衬底。 栅极设置在基板上。 源极掺杂区域形成在与栅极的第一侧相邻的衬底中，其中源极掺杂区域具有不同于第一导电类型的第二导电类型。 漏极掺杂区域形成在衬底中，与栅极的第一侧相对的第二侧相邻。 漏极掺杂区域由具有第一导电类型的多个第一掺杂区域和具有第二导电类型的多个第二掺杂区域构成，其中交替布置第一掺杂区域和第二掺杂区域。

    SEMICONDUCTOR DEVICE AND LATERAL DIFFUSED METAL-OXIDE-SEMICONDUCTOR TRANSISTOR
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND LATERAL DIFFUSED METAL-OXIDE-SEMICONDUCTOR TRANSISTOR 有权
    半导体器件和侧向扩散金属氧化物半导体晶体管

    公开(公告)号：US20100301388A1

    公开(公告)日：2010-12-02

    申请号：US12477054

    申请日：2009-06-02

    申请人： Jimmy Lin ,  Shang-Hui Tu ,  Ming-Horng Hsiao

    发明人： Jimmy Lin ,  Shang-Hui Tu ,  Ming-Horng Hsiao

    IPC分类号： H01L29/73 ,  H01L27/06

    CPC分类号： H01L29/7393 ,  H01L27/0262 ,  H01L29/0696 ,  H01L29/7436 ,  H01L29/87

    摘要： The invention provides a semiconductor device and a lateral diffused metal-oxide-semiconductor transistor. The semiconductor device includes a substrate having a first conductive type. A gate is disposed on the substrate. A source doped region is formed in the substrate, neighboring with a first side of the gate, wherein the source doped region has a second conductive type different from the first conductive type. A drain doped region is formed in the substrate, neighboring with a second side opposite to the first side of the gate. The drain doped region is constructed by a plurality of first doped regions with the first conductive type and a plurality of second doped regions with the second conductive type, wherein the first doped regions and the second doped regions are alternatively arranged.

    摘要翻译： 本发明提供一种半导体器件和横向漫射金属氧化物半导体晶体管。 半导体器件包括具有第一导电类型的衬底。 栅极设置在基板上。 源极掺杂区域形成在与栅极的第一侧相邻的衬底中，其中源极掺杂区域具有不同于第一导电类型的第二导电类型。 漏极掺杂区域形成在衬底中，与栅极的第一侧相对的第二侧相邻。 漏极掺杂区域由具有第一导电类型的多个第一掺杂区域和具有第二导电类型的多个第二掺杂区域构成，其中交替布置第一掺杂区域和第二掺杂区域。

    Method of fabricating a vertical diffusion metal-oxide-semiconductor transistor
    3.
    发明授权
    Method of fabricating a vertical diffusion metal-oxide-semiconductor transistor 有权
    制造垂直扩散金属氧化物半导体晶体管的方法

    公开(公告)号：US09076887B2

    公开(公告)日：2015-07-07

    申请号：US13464584

    申请日：2012-05-04

    申请人： Tsung-Hsiung Lee ,  Shang-Hui Tu ,  Rudy Octavius Sihombing

    发明人： Tsung-Hsiung Lee ,  Shang-Hui Tu ,  Rudy Octavius Sihombing

    IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/265 ,  H01L27/088

    CPC分类号： H01L21/823487 ,  H01L21/26586 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/7802

    摘要： A method for fabricating a semiconductor device is provided. A method for fabricating a semiconductor device includes providing a semiconductor substrate having a first conductive type. An epitaxy layer having the first conductive type is formed on the semiconductor substrate. First trenches are formed in the epitaxy layer. First insulating liner layers are formed on sidewalls and bottoms of the first trenches. A first dopant having the first conductive type dopes the epitaxy layer from the sidewalls of the first trenches to form first doped regions. A first insulating material is filled into the first trenches. Second trenches are formed in the epitaxy layer. Second insulating liner layers are formed on sidewalls and bottoms of the second trenches. A second dopant having a second conductive type dopes the epitaxy layer from the sidewalls of the second trenches to form second doped regions.

    摘要翻译： 提供一种制造半导体器件的方法。 一种制造半导体器件的方法包括提供具有第一导电类型的半导体衬底。 在半导体衬底上形成具有第一导电类型的外延层。 在外延层中形成第一沟槽。 第一绝缘衬垫层形成在第一沟槽的侧壁和底部上。 具有第一导电类型的第一掺杂剂从第一沟槽的侧壁掺杂外延层以形成第一掺杂区域。 第一绝缘材料被填充到第一沟槽中。 在外延层中形成第二沟槽。 第二绝缘衬垫层形成在第二沟槽的侧壁和底部上。 具有第二导电类型的第二掺杂剂从第二沟槽的侧壁掺杂外延层以形成第二掺杂区域。

    SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号：US20130175607A1

    公开(公告)日：2013-07-11

    申请号：US13419464

    申请日：2012-03-14

    申请人： Tsung-Hsiung Lee ,  Shang-Hui Tu

    发明人： Tsung-Hsiung Lee ,  Shang-Hui Tu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

    摘要： A semiconductor device is provided. The semiconductor device includes a substrate having a first doping region and an overlying second doping region, wherein the first and second doping regions have a first conductivity type and wherein the second doping region has at least one first trench and at least one second trench adjacent thereto. A first epitaxial layer is disposed in the first trench and has a second conductivity type. A second epitaxial layer is disposed in the second trench and has the first conductivity type, wherein the second epitaxial layer has a doping concentration greater than that of the second doping region and less than that of the first doping region. A gate structure is disposed on the second trench. A method of fabricating a semiconductor device is also disclosed.

    摘要翻译： 提供半导体器件。 半导体器件包括具有第一掺杂区和上覆第二掺杂区的衬底，其中第一和第二掺杂区具有第一导电类型，并且其中第二掺杂区具有至少一个第一沟槽和与其相邻的至少一个第二沟槽 。 第一外延层设置在第一沟槽中并且具有第二导电类型。 第二外延层设置在第二沟槽中并且具有第一导电类型，其中第二外延层的掺杂浓度大于第二掺杂区的掺杂浓度，并且小于第一掺杂区的掺杂浓度。 栅极结构设置在第二沟槽上。 还公开了制造半导体器件的方法。

    Semiconductor structure and fabrication method thereof
    7.
    发明授权
    Semiconductor structure and fabrication method thereof 有权
    半导体结构及其制造方法

    公开(公告)号：US08252652B2

    公开(公告)日：2012-08-28

    申请号：US12748703

    申请日：2010-03-29

    申请人： Yih-Jau Chang ,  Shang-Hui Tu ,  Gene Sheu ,  Yi-Fong Chang ,  Nithin Devarajulu Palavalli

    发明人： Yih-Jau Chang ,  Shang-Hui Tu ,  Gene Sheu ,  Yi-Fong Chang ,  Nithin Devarajulu Palavalli

    IPC分类号： H01L21/336 ,  H01L29/06

    CPC分类号： H01L29/7835 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66659

    摘要： A semiconductor structure is provided. A second conductivity type well region is formed on a first conductivity type substrate. A second conductivity type diffused source and second conductivity type diffused drain are formed on the first conductivity type substrate. A gate structure is formed on the second conductivity type well region between the second conductivity type diffused source and the second conductivity type diffused drain. First conductivity type buried rings are arranged in a horizontal direction, and formed in the second conductivity type well region, and divide the second conductivity type well region into an upper drift region and a lower drift region.

    摘要翻译： 提供半导体结构。 在第一导电型基板上形成第二导电类型阱区。 在第一导电型基板上形成第二导电型扩散源极和第二导电型扩散漏极。 在第二导电型扩散源和第二导电型扩散漏极之间的第二导电类型阱区上形成栅极结构。 第一导电型掩埋环沿水平方向布置，并形成在第二导电类型阱区中，并将第二导电类型阱区划分为上漂移区和下漂移区。

    HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH SCHOTTKY DIODES
    8.
    发明申请
    HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH SCHOTTKY DIODES 有权
    具有肖特基二极管的高压半导体器件

    公开(公告)号：US20100148253A1

    公开(公告)日：2010-06-17

    申请号：US12426194

    申请日：2009-04-17

    申请人： Shang-Hui Tu ,  Hung-Shern Tsai

    发明人： Shang-Hui Tu ,  Hung-Shern Tsai

    IPC分类号： H01L27/06

    CPC分类号： H01L29/7835 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/782

    摘要： High voltage semiconductor devices with Schottky diodes are presented. A high voltage semiconductor device includes an LDMOS device and a Schottky diode device. The LDMOS device includes a semiconductor substrate, a P-body region in a first region of the substrate, and an N-drift region in the second region of the substrate with a junction therebetween. A patterned isolation region defines an active region. An anode electrode is disposed on the P-body region. An N+-doped region is disposed in the N-drift region. A cathode electrode is disposed on the N+-doped region. The Schottky diode includes an N-drift region on the semiconductor substrate. The anode electrode is disposed on the N-drift region at the first region of the substrate. The N+-doped region is disposed on the N-drift region at the second region of the substrate. The cathode electrode is disposed on the N+-doped region.

    摘要翻译： 提出了具有肖特基二极管的高电压半导体器件。 高压半导体器件包括LDMOS器件和肖特基二极管器件。 LDMOS器件包括半导体衬底，衬底的第一区域中的P体区域和衬底的第二区域中的N漂移区域，其间具有接合部。 图案化隔离区限定有源区。 阳极电极设置在P体区域上。 N +掺杂区域设置在N漂移区域中。 在N +掺杂区域上设置阴极电极。 肖特基二极管包括半导体衬底上的N漂移区。 阳极电极设置在衬底的第一区域的N漂移区上。 N +掺杂区域设置在衬底的第二区域的N漂移区上。 阴极电极设置在N +掺杂区域上。

    Semiconductor structure and fabrication method thereof
    9.
    发明授权
    Semiconductor structure and fabrication method thereof 有权
    半导体结构及其制造方法

    公开(公告)号：US08669149B2

    公开(公告)日：2014-03-11

    申请号：US13473528

    申请日：2012-05-16

    申请人： Shang-Hui Tu ,  Hung-Shern Tsai

    发明人： Shang-Hui Tu ,  Hung-Shern Tsai

    IPC分类号： H01L21/337

    CPC分类号： H01L29/7835 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659

    摘要： A method for fabrication of a semiconductor device is provided. A first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the first type substrate with the second type bar regions between the second type well region and the first type doped body region. The first type doped body region, the second type well region, and each of the second type bar regions are separated from each other by the first type substrate. The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region. A second type heavily-doped region is formed in the second type well region.

    摘要翻译： 提供一种制造半导体器件的方法。 第一类型的掺杂体区域形成在第一类型的衬底中。 在第一类型掺杂体区域中形成第一类型的重掺杂区域。 第二类型阱区域和第二类型区域形成在第一类型衬底中，第二类型阱区域在第二类型阱区域和第一类型掺杂体区域之间。 第一类型掺杂体区域，第二类型阱区域和每个第二类型区域区域通过第一类型衬底彼此分离。 第二类型的杆区域是相互扩散的，以形成邻接第二类型井区域的第二类型的连续区域。 在第二类型阱区域中形成第二类型重掺杂区域。

    Electrostatic discharge protection device
    10.
    发明授权
    Electrostatic discharge protection device 有权
    静电放电保护装置

    公开(公告)号：US08008687B2

    公开(公告)日：2011-08-30

    申请号：US12472091

    申请日：2009-05-26

    申请人： Shang-Hui Tu ,  Hung-Shern Tsai

    发明人： Shang-Hui Tu ,  Hung-Shern Tsai

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7393 ,  H01L27/0262

    摘要： An electrostatic discharge protection device including a substrate, a first doped region, a first gate electrode, a second doped region, a second gate electrode, and a third doped region is disclosed. The substrate has a first conductive type. The first doped region has a second conductive type and is formed in the substrate. The first gate electrode is formed on the substrate. The second doped region has the second conductive type and is formed in the substrate. A transistor is constituted by the first doped region, the first gate electrode, and the second doped region. The second gate electrode is formed on the substrate. The first and the second gate electrodes are separated. The third doped region has the first conductive type and is formed in the substrate. A discharge element is constituted by the first doped region, the second gate electrode, and the third doped region.

    摘要翻译： 公开了一种包括衬底，第一掺杂区，第一栅电极，第二掺杂区，第二栅电极和第三掺杂区的静电放电保护器件。 衬底具有第一导电类型。 第一掺杂区具有第二导电类型并形成在衬底中。 第一栅电极形成在基板上。 第二掺杂区具有第二导电类型并形成在衬底中。 晶体管由第一掺杂区域，第一栅极电极和第二掺杂区域构成。 第二栅电极形成在基板上。 第一和第二栅电极分离。 第三掺杂区域具有第一导电类型并形成在衬底中。 放电元件由第一掺杂区域，第二栅极电极和第三掺杂区域构成。