公开(公告)号：US20120292672A1

公开(公告)日：2012-11-22

申请号：US13111741

申请日：2011-05-19

Applicant: Jin CHO

Inventor： Jin CHO

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L21/823431 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: FINFET ICs and methods for their fabrication are provided. In accordance with one embodiment a FINFET IC is fabricated by forming in a substrate a region doped with an impurity of a first doping type. The substrate region is etched to form a recess defining a fin having a height and sidewalls and the recess adjacent the fin is filled with an insulator having a thickness less than the height. Spacers are formed on the sidewalls and a portion of the insulator is etched to expose a portion of the sidewalls. The exposed portion of the sidewalls is doped with an impurity of the first doping type, the exposed sidewalls are oxidized, and the sidewall spacers are removed. A gate insulator and gate electrode are formed overlying the fin, and end portions of the fin are doped with an impurity of a second doping type to form source and drain regions.

Abstract translation: 提供FINFET IC及其制造方法。 根据一个实施例，通过在衬底中形成掺杂有第一掺杂类型的杂质的区域来制造FINFET IC。 蚀刻衬底区域以形成限定具有高度和侧壁的翅片的凹部，并且与翅片相邻的凹部填充有厚度小于该高度的绝缘体。 隔板形成在侧壁上，并且绝缘体的一部分被蚀刻以暴露侧壁的一部分。 侧壁的暴露部分掺杂有第一掺杂类型的杂质，暴露的侧壁被氧化，并且去除侧壁间隔物。 栅极绝缘体和栅电极形成在鳍的上方，并且鳍的端部掺杂有第二掺杂类型的杂质以形成源极和漏极区。

公开(公告)号：US20100248454A1

公开(公告)日：2010-09-30

申请号：US12413174

申请日：2009-03-27

Applicant: Witold MASZARA ,  Ming-Ren LIN ,  Jin CHO ,  Zoran KRIVOKAPIC

Inventor： Witold MASZARA ,  Ming-Ren LIN ,  Jin CHO ,  Zoran KRIVOKAPIC

IPC: H01L21/20 ,  H01L21/28

CPC classification number: H01L29/66795

Abstract: A method of manufacturing semiconductor fins for a semiconductor device may begin by providing a bulk semiconductor substrate. The method continues by growing a layer of first epitaxial semiconductor material on the bulk semiconductor substrate, and by growing a layer of second epitaxial semiconductor material on the layer of first epitaxial semiconductor material. The method then creates a fin pattern mask on the layer of second epitaxial semiconductor material. The fin pattern mask has features corresponding to a plurality of fins. Next, the method anisotropically etches the layer of second epitaxial semiconductor material, using the fin pattern mask as an etch mask, and using the layer of first epitaxial semiconductor material as an etch stop layer. This etching step results in a plurality of fins formed from the layer of second epitaxial semiconductor material.

Abstract translation: 制造用于半导体器件的半导体鳍片的方法可以通过提供体半导体衬底开始。 该方法通过在体半导体衬底上生长第一外延半导体材料层并通过在第一外延半导体材料层上生长第二外延半导体材料层来继续。 该方法然后在第二外延半导体材料层上产生鳍状图案掩模。 翅片图形掩模具有对应于多个翅片的特征。 接下来，使用鳍图案掩模作为蚀刻掩模，并且使用第一外延半导体材料层作为蚀刻停止层，该方法各向异性地蚀刻第二外延半导体材料的层。 该蚀刻步骤导致由第二外延半导体材料层形成的多个鳍片。

公开(公告)号：US20100295058A1

公开(公告)日：2010-11-25

申请号：US12468612

申请日：2009-05-19

Applicant: Jin CHO

Inventor： Jin CHO

IPC: H01L31/0312

CPC classification number: H01L29/7391 ,  B82Y10/00 ,  H01L29/122 ,  H01L29/66356 ,  H01L29/66431 ,  H01L29/66977 ,  H01L29/7782

Abstract: A tunneling field effect transistor (TFET) device includes a semiconductor substrate having a layer of relatively intermediate bandgap semiconductor material, a layer of relatively low bandgap semiconductor material overlying the layer of relatively intermediate bandgap semiconductor material, and a layer of relatively high bandgap semiconductor material overlying the layer of relatively low bandgap semiconductor material. The TFET device includes a source region, a drain region, and a channel region defined in the semiconductor substrate. The TFET device also has a gate structure overlying at least a portion of the channel region. The source region is highly doped with an impurity dopant having a first conductivity type, and the drain region is highly doped with an impurity dopant having a second conductivity type. The layer of relatively low bandgap semiconductor material promotes tunneling at a first junction between the source region and the channel region, and the layer of relatively high bandgap semiconductor material inhibits tunneling at a second junction between the source region and the channel region.

Abstract translation: 隧道场效应晶体管（TFET）器件包括具有相对中间带隙半导体材料的层的半导体衬底，覆盖在相对中间的带隙半导体材料层上的相对较低的带隙半导体材料的层以及相对较高的带隙半导体材料层 覆盖相对较低带隙半导体材料的层。 TFET器件包括源极区，漏极区和限定在半导体衬底中的沟道区。 TFET器件还具有覆盖沟道区域的至少一部分的栅极结构。 源区高掺杂有具有第一导电类型的杂质掺杂剂，并且漏区被高掺杂有具有第二导电类型的杂质掺杂物。 相对低的带隙半导体材料的层促进在源极区域和沟道区域之间的第一接合处的隧穿，并且相对较高的带隙半导体材料的层在源极区域和沟道区域之间的第二结点处抑制隧穿。