摘要:
Aspects of the disclosure provide a method for detecting marks. The method includes receiving a data signal from a channel. Further, the method includes matching the data signal to a template that corresponds to a predetermined pattern transmitted over the channel to detect marks, prior to decoding the data signal into a decoded bit stream.
摘要:
A system with a nonlinear element processes a replay signal with a scaling factor into a signal compensated for asymmetry. The replay signal may include data from an optical disk. The scaling factor may be estimated based on the compensated signal and a scaling factor gain. The replay signal and the compensated signal may be converted into digital signals and processed digitally. In one embodiment, the compensated signal may be calculated as approximately the scaling factor multiplied by a square of an amplitude of the replay signal added to the amplitude of the replay signal. In another embodiment, the compensated signal may be calculated as approximately the scaling factor multiplied by an absolute value of an amplitude of the replay signal added to the amplitude of the replay signal. A related method is also disclosed. Other embodiments are provided, and each of the embodiments described herein can be used alone or in combination with one another.
摘要:
Aspects of the disclosure provide a signal processing circuit that has fast response time to sudden profile changes in an electrical signal. The signal processing circuit includes a processing path configured to process an electrical signal that is generated in response to reading data on a storage medium, and a feed-forward correction module. The feed-forward correction module is configured to detect a profile variation based the electrical signal in a time window, and correct the electrical signal in the time window based on the detected profile variation.
摘要:
Aspects of the disclosure provide a signal processing circuit that includes a signal processing circuit includes a processing path configured to process an electrical signal to produce input data samples, and a feed-forward correction module configured to delay the input data samples to produce delayed data samples, to apply the delayed data samples to a timing loop during periods when a profile variation of the data samples is not detected, and to apply the input data sample to the timing loop during periods when a profile variation of the data samples is detected.
摘要:
Aspects of the disclosure provide a signal processing circuit to reduce signal distortions due to optical aberrations. The signal processing circuit includes a circuit configured to receive an electrical signal corresponding to a light beam reflected by a storage medium and filter the electrical signal to reduce distortions due to, for example, birefringence aberration in the light beam, and an equalizer configured to equalize the filtered electrical signal. In an example, the circuit is a median filter.
摘要:
A method and device for determining frequency error to extend the pull-in range of a timing recovery circuit for a storage device such as an optical disc drive. A code associated with a storage format of the storage device is detected, and the distance between occurrences of the code is determined. The calculated distance is compared with the expected distance to determine the difference. Based on the difference, the frequency error is determined.
摘要:
Methods and systems for compensating reducing jitter produced by a phase-locked loop are disclosed. For example, in a particular embodiment, a phase-locked loop device for reducing jitter may include a voltage-control oscillator (VCO) signal configured to produce a VCO signal, phase-detection circuitry configured to compare an input signal and the VCO signal to produce a phase error signal, and slew-rate limiting circuitry configured to receive the phase error signal and apply a slew-rate limit process on the phase error signal to produce a modified error signal.
摘要:
A decoding system includes a decoder, a first module and a second module. The decoder is configured to receive data read from an optical storage medium and perform a first decoding iteration and a second decoding iteration to decode the data. The first decoding iteration includes generating a resultant matrix. The first module is configured to, based on first decoding statuses of multiple bytes in the resultant matrix, determine second decoding statuses of bytes proximate to failed bytes of a feedback matrix. The feedback matrix is generated based on the resultant matrix. The first module is configured to mark selected ones of the failed bytes as erasures based on the second decoding statuses. The second module is configured to correct one or more of the bytes marked as erasures during the second decoding iteration.
摘要:
Aspects of the disclosure provide a signal processing circuit to reconstruct data from an analog signal. The signal processing circuit includes an analog to digital converter (ADC), an equalizer, a first timing compensation module, a phase-shift module and a second timing compensation module. The ADC receives an analog input signal, samples the analog input signal based on a sampling clock signal, and converts the sampled analog input signal into a digital output signal. The equalizer equalizes the digital output signal. The first timing compensation module detects a first timing error based on the digital output signal, and adjusts the sampling clock signal based on the first timing error. The phase-shift module phase-shifts the equalized digital output signal based on a phase-shift signal. The second timing compensation module detects a second timing error based on the equalized digital output signal, and adjusts the phase-shift signal based on the second timing error.
摘要:
A media defect compensation system and method may decouple effects of asymmetry from baseline error compensation computations. In some embodiments, a switching mechanism passes a baseline error signal into a baseline loop when a determination is made that a baseline error signal is not affected by asymmetry, and otherwise freezes the baseline loop when asymmetry may influence baseline error calculations.