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    TRANSISTORS HAVING A CHANNEL REGION BETWEEN CHANNEL-PORTION HOLES AND METHODS OF FORMING THE SAME
    3.
    发明申请
    TRANSISTORS HAVING A CHANNEL REGION BETWEEN CHANNEL-PORTION HOLES AND METHODS OF FORMING THE SAME 失效
    在通道孔之间具有通道区域的晶体管及其形成方法

    公开(公告)号：US20090114967A1

    公开(公告)日：2009-05-07

    申请号：US12345415

    申请日：2008-12-29

    申请人： Jin-Woo Lee ,  Tae-Young Chung ,  Yong-Sung Kim

    发明人： Jin-Woo Lee ,  Tae-Young Chung ,  Yong-Sung Kim

    IPC分类号： H01L27/108 ,  H01L49/00

    CPC分类号： H01L29/66659 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7835

    摘要： According to some embodiments of the invention, transistors have channel regions between channel-portion holes. Methods of forming the same include at least two channel-portion holes disposed in a semiconductor substrate. Line patterns are formed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate to fill the channel-portion holes. A channel region is disposed in the semiconductor substrate below the line patterns. At this time, the channel region is formed between the channel-portion holes and also covers lower portions of the channel-portion holes. Driving current capability and refresh characteristics of DRAMs utilizing the inventive transistors are improved.

    摘要翻译： 根据本发明的一些实施例，晶体管在沟道部分孔之间具有沟道区。 形成它们的方法包括设置在半导体衬底中的至少两个通道部分孔。 线图案平行地形成为在半导体衬底的主表面上彼此间隔开以填充沟道部分孔。 沟道区域设置在半导体衬底中的线图案下方。 此时，通道区域形成在通道部分孔之间并且还覆盖通道部分孔的下部。 利用本发明晶体管驱动DRAM的驱动电流能力和刷新特性得到改善。

    Transistors having a channel region between channel-portion holes and methods of forming the same
    5.
    发明授权
    Transistors having a channel region between channel-portion holes and methods of forming the same 失效
    在通道部分孔之间具有沟道区的晶体管及其形成方法

    公开(公告)号：US08039895B2

    公开(公告)日：2011-10-18

    申请号：US12345415

    申请日：2008-12-29

    申请人： Jin-Woo Lee ,  Tae-Young Chung ,  Yong-Sung Kim

    发明人： Jin-Woo Lee ,  Tae-Young Chung ,  Yong-Sung Kim

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66659 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7835

    摘要： According to some embodiments of the invention, transistors have channel regions between channel-portion holes. Methods of forming the same include at least two channel-portion holes disposed in a semiconductor substrate. Line patterns are formed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate to fill the channel-portion holes. A channel region is disposed in the semiconductor substrate below the line patterns. At this time, the channel region is formed between the channel-portion holes and also covers lower portions of the channel-portion holes. Driving current capability and refresh characteristics of DRAMs utilizing the inventive transistors are improved.

    摘要翻译： 根据本发明的一些实施例，晶体管在沟道部分孔之间具有沟道区。 形成它们的方法包括设置在半导体衬底中的至少两个通道部分孔。 线图案平行地形成为在半导体衬底的主表面上彼此间隔开以填充沟道部分孔。 沟道区域设置在半导体衬底中的线图案下方。 此时，通道区域形成在通道部分孔之间并且还覆盖通道部分孔的下部。 利用本发明晶体管驱动DRAM的驱动电流能力和刷新特性得到改善。

    Transistors having a channel region between channel-portion holes and methods of forming the same
    6.
    发明授权
    Transistors having a channel region between channel-portion holes and methods of forming the same 失效
    在通道部分孔之间具有沟道区的晶体管及其形成方法

    公开(公告)号：US07492004B2

    公开(公告)日：2009-02-17

    申请号：US11054104

    申请日：2005-02-08

    申请人： Jin-Woo Lee ,  Tae-Young Chung ,  Yong-Sung Kim

    发明人： Jin-Woo Lee ,  Tae-Young Chung ,  Yong-Sung Kim

    IPC分类号： H01L29/94

    CPC分类号： H01L29/66659 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7835

    摘要： According to some embodiments of the invention, transistors have channel regions between channel-portion holes. Methods of forming the same include at least two channel-portion holes disposed in a semiconductor substrate. Line patterns are formed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate to fill the channel-portion holes. A channel region is disposed in the semiconductor substrate below the line patterns. At this time, the channel region is formed between the channel-portion holes and also covers lower portions of the channel-portion holes. Driving current capability and refresh characteristics of DRAMs utilizing the inventive transistors are improved.

    摘要翻译： 根据本发明的一些实施例，晶体管在沟道部分孔之间具有沟道区。 形成它们的方法包括设置在半导体衬底中的至少两个通道部分孔。 线图案平行地形成为在半导体衬底的主表面上彼此间隔开以填充沟道部分孔。 沟道区域设置在半导体衬底中的线图案下方。 此时，通道区域形成在通道部分孔之间并且还覆盖通道部分孔的下部。 利用本发明晶体管驱动DRAM的驱动电流能力和刷新特性得到改善。

    Semiconductor devices including transistors having recessed channels and methods of fabricating the same
    7.
    发明申请
    Semiconductor devices including transistors having recessed channels and methods of fabricating the same 失效
    包括具有凹陷通道的晶体管的半导体器件及其制造方法

    公开(公告)号：US20080001230A1

    公开(公告)日：2008-01-03

    申请号：US11704872

    申请日：2007-02-09

    申请人： Jin-Woo Lee ,  Tae-Young Chung ,  Sung-Hee Han

    发明人： Jin-Woo Lee ,  Tae-Young Chung ,  Sung-Hee Han

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/78 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621

    摘要： Semiconductor devices including an isolation layer on a semiconductor substrate are provided. The isolation layer defines an active region of the semiconductor substrate. The device further includes an upper gate electrode crossing over the active region and extending to the isolation layer and lower active gate electrode. The lower active gate electrode includes a first active gate electrode extending from the upper gate electrode to the active region and a second active gate electrode below the first active gate electrode and having a greater width than a width of the first active gate electrode. The device further includes a lower field gate electrode that extends from the upper gate electrode to the isolation layer and has a bottom surface that is at a lower level than a bottom surface of the active gate electrode such that the sidewalls of the active region are covered below the lower active gate electrode. Related methods of fabricating semiconductor devices are also provided herein.

    摘要翻译： 提供包括半导体衬底上的隔离层的半导体器件。 隔离层限定半导体衬底的有源区。 该器件还包括与有源区交叉并延伸到隔离层和下活性栅电极的上栅电极。 下有源栅电极包括从上栅极延伸到有源区的第一有源栅电极和位于第一有源栅电极下方并且具有比第一有源栅电极的宽度更大的宽度的第二有源栅电极。 该器件还包括一个从上部栅电极延伸到隔离层的下部栅极电极，并且具有一底部表面，该底表面处于与该有源栅极电极的底表面相比较低的位置，使得该有源区域的侧壁被覆盖 在下部有源栅电极下方。 本文还提供了制造半导体器件的相关方法。

    Recessed channel transistor
    9.
    发明授权
    Recessed channel transistor 失效
    嵌入式沟道晶体管

    公开(公告)号：US07893487B2

    公开(公告)日：2011-02-22

    申请号：US12314582

    申请日：2008-12-12

    申请人： Jin-Woo Lee ,  Tae-Young Chung ,  Joo-Young Lee

    发明人： Jin-Woo Lee ,  Tae-Young Chung ,  Joo-Young Lee

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/66621 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823437 ,  H01L29/1037 ,  H01L29/105 ,  H01L29/4236

    摘要： A recessed channel transistor includes a single crystalline silicon substrate having a recessed portion, a bottom surface of the recessed portion including an elevated central portion, a channel doping region in the single crystalline silicon substrate, the channel doping region being under the bottom surface of the recessed portion, a gate structure in the recessed portion, and source/drain regions in the single crystalline silicon substrate at both sides of the recessed portion, the source/drain regions being spaced apart from the bottom surface of the recessed portion.

    摘要翻译： 凹陷沟道晶体管包括具有凹陷部分的单晶硅衬底，凹部的底表面包括升高的中心部分，在单晶硅衬底中的沟道掺杂区域，沟道掺杂区域位于 凹陷部分，凹陷部分中的栅极结构以及在凹陷部分两侧的单晶硅衬底中的源极/漏极区域，源极/漏极区域与凹陷部分的底表面间隔开。

    Methods of fabricating semiconductor devices including transistors having recessed channels
    10.
    发明授权
    Methods of fabricating semiconductor devices including transistors having recessed channels 失效
    制造包括具有凹槽的晶体管的半导体器件的方法

    公开(公告)号：US07666743B2

    公开(公告)日：2010-02-23

    申请号：US11704872

    申请日：2007-02-09

    申请人： Jin-Woo Lee ,  Tae-Young Chung ,  Sung-Hee Han

    发明人： Jin-Woo Lee ,  Tae-Young Chung ,  Sung-Hee Han

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621

    摘要： Semiconductor devices including an isolation layer on a semiconductor substrate are provided. The isolation layer defines an active region of the semiconductor substrate. The device further includes an upper gate electrode crossing over the active region and extending to the isolation layer and lower active gate electrode. The lower active gate electrode includes a first active gate electrode extending from the upper gate electrode to the active region and a second active gate electrode below the first active gate electrode and having a greater width than a width of the first active gate electrode. The device further includes a lower field gate electrode that extends from the upper gate electrode to the isolation layer and has a bottom surface that is at a lower level than a bottom surface of the active gate electrode such that the sidewalls of the active region are covered below the lower active gate electrode. Related methods of fabricating semiconductor devices are also provided herein.

    摘要翻译： 提供包括半导体衬底上的隔离层的半导体器件。 隔离层限定了半导体衬底的有源区。 该器件还包括与有源区交叉并延伸到隔离层和下活性栅电极的上栅电极。 下有源栅电极包括从上栅极延伸到有源区的第一有源栅电极和位于第一有源栅电极下方并且具有比第一有源栅电极的宽度更大的宽度的第二有源栅电极。 该器件还包括一个从上部栅电极延伸到隔离层的下部栅极电极，并且具有一底部表面，该底表面处于与该有源栅极电极的底表面相比较低的位置，使得该有源区域的侧壁被覆盖 在下部有源栅电极下方。 本文还提供了制造半导体器件的相关方法。