公开(公告)号：US07800944B2

公开(公告)日：2010-09-21

申请号：US12129820

申请日：2008-05-30

申请人： Jin-Young Chun ,  Jae-Yong Jeong ,  Chi-Weon Yoon

发明人： Jin-Young Chun ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： Disclosed is a nonvolatile memory device and programming method of a nonvolatile memory device. The programming method of the nonvolatile memory device includes conducting a first programming operation for a memory cell, retrieving original data from the memory cell after the first programming operation, and conducting a second programming operation with reference to the original data and a second verifying voltage higher than a first verifying voltage of the first programming operation.

摘要翻译： 公开了一种非易失性存储器件的非易失性存储器件和编程方法。 非易失性存储器件的编程方法包括对存储器单元执行第一编程操作，在第一编程操作之后从存储单元检索原始数据，并参考原始数据和第二验证电压进行第二编程操作 比第一编程操作的第一验证电压。

公开(公告)号：US07580281B2

公开(公告)日：2009-08-25

申请号：US11969969

申请日：2008-01-07

申请人： Jin-Young Chun ,  Jae-Yong Jeong ,  Chi-Weon Yoon

发明人： Jin-Young Chun ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC分类号： G11C11/34

CPC分类号： G11C16/22

摘要： A flash memory device and a related method of write protecting data are disclosed. The flash memory device includes a protection controller having a latch circuit storing temporary protected/accessible data, a cell array storing persistent protected/accessible data, a write controller altering the persistent protected/accessible data, and a latch controller altering the temporary protected/accessible data.

摘要翻译： 公开了一种闪存设备和写保护数据的相关方法。 闪存设备包括保护控制器，其具有存储临时保护/可访问数据的锁存电路，存储持久保护/可访问数据的单元阵列，改变永久保护/可访问数据的写控制器以及改变临时保护/可访问的锁存器控制器 数据。

公开(公告)号：US07787305B2

公开(公告)日：2010-08-31

申请号：US12134648

申请日：2008-06-06

申请人： In-Mo Kim ,  Jae-Yong Jeong ,  Chi-Weon Yoon

发明人： In-Mo Kim ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation, a bulk-voltage supply circuit configured to supply a bulk voltage into a bulk of the flash memory cell array and a writing circuit configured to drive the bit lines selected by conditions during a programming operation. A control logic block is configured to control the writing circuit and the bulk-voltage supply circuit during the programming operation. The control logic block is configured to cause the writing circuit and/or the bulk-voltage supply circuit to change at least one of the conditions of the writing circuit and/or the bulk voltage responsive to the selected step increment.

摘要翻译： 一种闪速存储器件包括：闪存单元阵列，具有布置有字线和位线的闪速存储器单元;字线驱动器电路，被配置为在编程操作期间以选定的阶跃增量驱动所述字线，所述体电压电源电路被配置为 将大容量电压提供到闪存单元阵列的大部分中;以及写入电路，其被配置为驱动在编程操作期间由条件选择的位线。 控制逻辑块被配置为在编程操作期间控制写入电路和体电压电源电路。 控制逻辑块被配置为使得写入电路和/或体电压电源电路响应于所选择的步进增量来改变写入电路和/或体电压的条件中的至少一个。

公开(公告)号：US07474566B2

公开(公告)日：2009-01-06

申请号：US11763606

申请日：2007-06-15

申请人： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

发明人： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC分类号： G11C16/06

CPC分类号： G11C16/3454

摘要： A method of driving a non-volatile memory device includes programming a plurality of memory cells based on a first data copied from a program data buffer to a verification data buffer, verifying the memory cells by overwriting a result of the verification of the programmed memory cells to a verification data buffer, and re-verifying the memory cells by repeating the programming and verifying operations at least once with respect to the memory cells that were successfully verified, based on the verification result written to the verification data buffer. A non-volatile memory device includes a program data buffer storing first data, a verification data buffer copying and storing the first data, a plurality of memory cells programmed based on the data stored in the verification data buffer, a comparator comparing data stored in the verification data buffer with data read out from the programmed memory cells and outputting comparison data generated based on a result of the comparison to the verification data buffer, and a control unit controlling the program data buffer, the verification data buffer, the memory cells, and the comparator to additionally program or verify the memory cells that were successfully verified, based on the first data.

摘要翻译： 驱动非易失性存储器件的方法包括：基于从程序数据缓冲器复制到验证数据缓冲器的第一数据来编程多个存储器单元，通过覆盖编程的存储器单元的验证结果来验证存储器单元 并且基于写入验证数据缓冲器的验证结果，通过重复对相对于成功验证的存储器单元的编程和验证操作至少一次来重新验证存储器单元。 非易失性存储装置包括存储第一数据的程序数据缓冲器，复制和存储第一数据的验证数据缓冲器，基于存储在验证数据缓冲器中的数据编程的多个存储器单元，比较存储在验证数据缓冲器中的数据的比较器 验证数据缓冲器，其具有从编程的存储器单元读出的数据，并输出基于与验证数据缓冲器的比较结果生成的比较数据;以及控制单元，控制程序数据缓冲器，验证数据缓冲器，存储器单元和 所述比较器基于所述第一数据额外编程或验证已成功验证的存储器单元。

公开(公告)号：US20090003075A1

公开(公告)日：2009-01-01

申请号：US12134648

申请日：2008-06-06

申请人： In-Mo Kim ,  Jae-Yong Jeong ,  Chi-Weon Yoon

发明人： In-Mo Kim ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC分类号： G11C16/06

CPC分类号： G11C16/10

摘要： A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation, a bulk-voltage supply circuit configured to supply a bulk voltage into a bulk of the flash memory cell array and a writing circuit configured to drive the bit lines selected by conditions during a programming operation. A control logic block is configured to control the writing circuit and the bulk-voltage supply circuit during the programming operation. The control logic block is configured to cause the writing circuit and/or the bulk-voltage supply circuit to change at least one of the conditions of the writing circuit and/or the bulk voltage responsive to the selected step increment.

摘要翻译： 一种闪速存储器件包括：闪存单元阵列，具有布置有字线和位线的闪速存储器单元;字线驱动器电路，被配置为在编程操作期间以选定的阶跃增量驱动所述字线，所述体电压电源电路被配置为 将大容量电压提供到闪存单元阵列的大部分中;以及写入电路，其被配置为驱动在编程操作期间由条件选择的位线。 控制逻辑块被配置为在编程操作期间控制写入电路和体电压电源电路。 控制逻辑块被配置为使得写入电路和/或体电压电源电路响应于所选择的步进增量来改变写入电路和/或体电压的条件中的至少一个。

公开(公告)号：US20080056006A1

公开(公告)日：2008-03-06

申请号：US11642925

申请日：2006-12-21

申请人： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

发明人： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： A method for programming a flash memory device is provided, where the flash memory device includes a plurality of memory cells, and where a threshold voltage of each of the memory cells is programmable in any one of plural corresponding data states. The method includes programming selected memory cells in a first data state, verifying a result of the programming, successively programming selected memory cells in at least two or more data states corresponding to threshold voltages which are lower than a corresponding threshold voltage of the first data state, and verifying results of the successive programming

摘要翻译： 提供一种用于对闪速存储器件进行编程的方法，其中闪速存储器件包括多个存储器单元，并且其中每个存储器单元的阈值电压可以以多个对应的数据状态中的任何一个来编程。 该方法包括以第一数据状态编程所选择的存储器单元，验证编程结果，以对应于低于第一数据状态的对应阈值电压的阈值电压的至少两个或多个数据状态连续地编程所选择的存储器单元 ，并验证连续编程的结果

公开(公告)号：US07602650B2

公开(公告)日：2009-10-13

申请号：US11847388

申请日：2007-08-30

申请人： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

发明人： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC分类号： G11C11/34

CPC分类号： G11C8/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： In one aspect, a program method is provided for a flash memory device including a plurality of memory cells each being programmed in one of a plurality of data states. The program method of this aspect includes programming selected memory cells in a first data state, verifying a result of the programming, successively programming selected memory cells in at least two or more data states corresponding to threshold voltages which are lower than a threshold voltage corresponding to the first data state, and verifying results of the successive programming.

摘要翻译： 在一个方面，提供了一种用于闪存器件的程序方法，其包括多个存储器单元，每个存储器单元以多个数据状态中的一个被编程。 该方面的程序方法包括以第一数据状态编程所选择的存储单元，验证编程结果，以对应于低于对应于阈值电压的阈值电压的阈值电压的至少两个或多个数据状态连续地编程所选存储单元 第一数据状态，以及验证连续编程的结果。

公开(公告)号：US20080055998A1

公开(公告)日：2008-03-06

申请号：US11847388

申请日：2007-08-30

申请人： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

发明人： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C8/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： In one aspect, a program method is provided for a flash memory device including a plurality of memory cells each being programmed in one of a plurality of data states. The program method of this aspect includes programming selected memory cells in a first data state, verifying a result of the programming, successively programming selected memory cells in at least two or more data states corresponding to threshold voltages which are lower than a threshold voltage corresponding to the first data state, and verifying results of the successive programming.

摘要翻译： 在一个方面，提供了一种用于闪存器件的程序方法，其包括多个存储器单元，每个存储器单元以多个数据状态中的一个被编程。 该方面的程序方法包括以第一数据状态编程所选择的存储单元，验证编程结果，以对应于低于对应于阈值电压的阈值电压的阈值电压的至少两个或多个数据状态连续地编程所选存储单元 第一数据状态，以及验证连续编程的结果。

公开(公告)号：US07525838B2

公开(公告)日：2009-04-28

申请号：US11642925

申请日：2006-12-21

申请人： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

发明人： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： A method for programming a flash memory device is provided, where the flash memory device includes a plurality of memory cells, and where a threshold voltage of each of the memory cells is programmable in any one of plural corresponding data states. The method includes programming selected memory cells in a first data state, verifying a result of the programming, successively programming selected memory cells in at least two or more data states corresponding to threshold voltages which are lower than a corresponding threshold voltage of the first data state, and verifying results of the successive programming.

摘要翻译： 提供一种用于对闪速存储器件进行编程的方法，其中闪速存储器件包括多个存储器单元，并且其中每个存储器单元的阈值电压可以以多个对应的数据状态中的任何一个来编程。 该方法包括以第一数据状态编程所选择的存储器单元，验证编程结果，以对应于低于第一数据状态的对应阈值电压的阈值电压的至少两个或多个数据状态连续地编程所选择的存储器单元 ，并验证连续编程的结果。

公开(公告)号：US20080158993A1

公开(公告)日：2008-07-03

申请号：US11763606

申请日：2007-06-15

申请人： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

发明人： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC分类号： G11C16/28

CPC分类号： G11C16/3454

摘要： A method of driving a non-volatile memory device includes programming a plurality of memory cells based on a first data copied from a program data buffer to a verification data buffer, verifying the memory cells by overwriting a result of the verification of the programmed memory cells to a verification data buffer, and re-verifying the memory cells by repeating the programming and verifying operations at least once with respect to the memory cells that were successfully verified, based on the verification result written to the verification data buffer. A non-volatile memory device includes a program data buffer storing first data, a verification data buffer copying and storing the first data, a plurality of memory cells programmed based on the data stored in the verification data buffer, a comparator comparing data stored in the verification data buffer with data read out from the programmed memory cells and outputting comparison data generated based on a result of the comparison to the verification data buffer, and a control unit controlling the program data buffer, the verification data buffer, the memory cells, and the comparator to additionally program or verify the memory cells that were successfully verified, based on the first data.

摘要翻译： 驱动非易失性存储器件的方法包括：基于从程序数据缓冲器复制到验证数据缓冲器的第一数据来编程多个存储器单元，通过覆盖编程的存储器单元的验证结果来验证存储器单元 并且基于写入验证数据缓冲器的验证结果，通过重复对相对于成功验证的存储器单元的编程和验证操作至少一次来重新验证存储器单元。 非易失性存储装置包括存储第一数据的程序数据缓冲器，复制和存储第一数据的验证数据缓冲器，基于存储在验证数据缓冲器中的数据编程的多个存储器单元，比较存储在验证数据缓冲器中的数据的比较器 验证数据缓冲器，其具有从编程的存储器单元读出的数据，并输出基于与验证数据缓冲器的比较结果生成的比较数据;以及控制单元，控制程序数据缓冲器，验证数据缓冲器，存储器单元和 所述比较器基于所述第一数据额外编程或验证已成功验证的存储器单元。