利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

16 条记录 (耗时 0.02 秒)

    FIELD SEQUENTIAL COLOR DISPLAY
    1.
    发明申请
    FIELD SEQUENTIAL COLOR DISPLAY 审中-公开
    现场顺序颜色显示

    公开(公告)号：US20150070256A1

    公开(公告)日：2015-03-12

    申请号：US14397320

    申请日：2012-07-20

    申请人： Jing Gu ,  XIXI Lou

    发明人： Jing Gu ,  XIXI Lou

    IPC分类号： G09G3/34 ,  G09G3/36

    CPC分类号： G09G3/3413 ,  G09G3/3611 ,  G09G3/3674 ,  G09G2310/0218 ,  G09G2310/0235 ,  G09G2310/0283 ,  G09G2320/0242

    摘要： An apparatus includes control logic and a scan driving unit. The control logic is configured to control driving of a display panel having an array of pixels divided into groups of pixels. Each group of pixies includes rows of pixels. The control logic is configured to control sequentially applying of multiple backlights having different colors to the array of pixels in multiple time periods. The scan driving unit is operatively coupled to the control logic and is configured to, in each time period, scan the rows of pixels of each group of pixels according to a row scanning sequence. For each group of pixels, in a first time period, the scan driving unit sequentially scans the rows of pixels according to a first row scanning sequence; in a second time period, the scan driving unit sequentially scans the rows of pixels according to a second row scanning sequence.

    摘要翻译： 一种装置包括控制逻辑和扫描驱动单元。 控制逻辑被配置为控制具有被划分成像素组的像素阵列的显示面板的驱动。 每组小精灵包括像素行。 控制逻辑被配置为在多个时间段内顺序地应用具有不同颜色的多个背光源到像素阵列。 扫描驱动单元可操作地耦合到控制逻辑，并且被配置为在每个时间段中根据行扫描序列扫描每组像素的像素行。 对于每组像素，在第一时间段中，扫描驱动单元根据第一行扫描顺序依次扫描像素行; 在第二时间段中，扫描驱动单元根据第二行扫描顺序依次扫描像素行。

    Memory array
    2.
    发明授权
    Memory array 有权
    内存阵列

    公开(公告)号：US08693243B2

    公开(公告)日：2014-04-08

    申请号：US13253855

    申请日：2011-10-05

    申请人： Jing Gu ,  Bo Zhang ,  Weiran Kong ,  Jian Hu

    发明人： Jing Gu ,  Bo Zhang ,  Weiran Kong ,  Jian Hu

    IPC分类号： G11C11/34

    CPC分类号： G11C16/26 ,  G11C16/0458 ,  G11C16/10 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/7887

    摘要： A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.

    摘要翻译： 在半导体技术领域中使用的存储器阵列包括多个存储单元，位线，垂直于位线的字线和第一/第二控制线。 存储器阵列使用分裂门存储器单元，其中存储器单元的两个存储器位单元共享一个字线，从而可以通过向字线施加不同的电压来实现存储器单元的读取，编程和擦除，两个控制栅极 和源极/漏极区域; 字线共享结构使得分闸器闪存能够有效地减小芯片面积并避免过度擦除问题，同时保持芯片的电隔离性能不变，而不会增加工艺的复杂性。

    Memory Array
    3.
    发明申请
    Memory Array 有权
    内存阵列

    公开(公告)号：US20120206969A1

    公开(公告)日：2012-08-16

    申请号：US13253855

    申请日：2011-10-05

    申请人： Jing Gu ,  Bo Zhang ,  Weiran Kong ,  Jian Hu

    发明人： Jing Gu ,  Bo Zhang ,  Weiran Kong ,  Jian Hu

    IPC分类号： G11C16/04 ,  H01L29/788

    CPC分类号： G11C16/26 ,  G11C16/0458 ,  G11C16/10 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/7887

    摘要： A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.

    摘要翻译： 在半导体技术领域中使用的存储器阵列包括多个存储单元，位线，垂直于位线的字线和第一/第二控制线。 存储器阵列使用分裂门存储器单元，其中存储器单元的两个存储器位单元共享一个字线，从而可以通过向字线施加不同的电压来实现存储器单元的读取，编程和擦除，两个控制栅极 和源极/漏极区域; 字线共享结构使得分闸器闪存能够有效地减小芯片面积并避免过度擦除问题，同时保持芯片的电隔离性能不变，而不会增加工艺的复杂性。

    Hybrid streaming and downloading DRM in mobile networks
    4.
    发明授权
    Hybrid streaming and downloading DRM in mobile networks 有权
    在移动网络中混合流式传输和下载DRM

    公开(公告)号：US08191163B1

    公开(公告)日：2012-05-29

    申请号：US12163321

    申请日：2008-06-27

    申请人： Yaojun Sun ,  Jing Gu

    发明人： Yaojun Sun ,  Jing Gu

    IPC分类号： H04L29/06

    CPC分类号： H04L63/102 ,  H04L65/4084 ,  H04L2463/101

    摘要： Methods, systems, and media are provided for rights protection of an instance of media content in a hybrid downloading and streaming media environment. A request from a device to download an instance of media content is communicated. Verification is obtained as to whether or not the device is authorized to receive and execute the instance. The instance of media content is streamed so that portions may be downloaded. The instance of media content also includes interspersed, non-storable authorization information. When subsequent execution of the instance of stored media content is attempted, a subsequent request for the authorization information is communicated. Only the authorization information is streamed for the subsequent request, allowing execution without burdening network resources with data-intensive streams.

    摘要翻译： 提供方法，系统和媒体用于在混合下载和流媒体环境中的媒体内容实例的权限保护。 传送从设备下载媒体内容实例的请求。 获取设备是否被授权接收和执行该实例的验证。 流媒体内容的实例可以下载部分。 媒体内容的实例还包括散布的，不可存储的授权信息。 当尝试后续执行所存储的媒体内容的实例时，传送对授权信息的后续请求。 只有授权信息被流式传输以用于后续请求，允许执行而不会使数据密集型流浪费网络资源。

    GATE-SEPARATED TYPE FLASH MEMORY WITH SHARED WORD LINE
    5.
    发明申请
    GATE-SEPARATED TYPE FLASH MEMORY WITH SHARED WORD LINE 审中-公开
    具有共享字线的GATE分离型闪存

    公开(公告)号：US20110038214A1

    公开(公告)日：2011-02-17

    申请号：US12988852

    申请日：2009-05-13

    申请人： Jing Gu

    发明人： Jing Gu

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0458 ,  H01L29/40114 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7887

    摘要： A gate-separated type flash memory with a shared word line includes: a semiconductor substrate, on which a source electrode area and a drain electrode area are separately arranged; a word line, which is arranged between the source electrode area and the drain electrode area; a first storage bit unit, which is arranged between the word line and the source electrode area, and a second storage bit unit, which is arranged between the word line and the drain electrode area. The two storage bit units and word line are separated by a tunneling oxide layer. The two storage bit units respectively have a first control gate, a first floating gate and a second control gate, a second floating gate, and the two control gates are separately respectively arranged on two floating gates.

    摘要翻译： 具有共用字线的分闸式闪速存储器包括：半导体衬底，源电极区域和漏电极区域分别设置在该半导体衬底上; 位于源电极区域和漏电极区域之间的字线; 布置在字线和源电极区之间的第一存储位单元和布置在字线和漏电极区之间的第二存储位单元。 两个存储位单元和字线被隧道氧化物层分开。 两个存储位单元分别具有第一控制栅极，第一浮置栅极和第二控制栅极，第二浮动栅极，并且两个控制栅极分别分别布置在两个浮动栅极上。

    Easy Process Modeling Platform
    7.
    发明申请
    Easy Process Modeling Platform 有权
    简易过程建模平台

    公开(公告)号：US20130060596A1

    公开(公告)日：2013-03-07

    申请号：US13293965

    申请日：2011-11-10

    申请人： Jing Gu ,  Dong Wang ,  Yang Wang

    发明人： Jing Gu ,  Dong Wang ,  Yang Wang

    IPC分类号： G06Q10/06

    CPC分类号： G06Q10/0633 ,  G06Q10/06

    摘要： The present disclosure describes methods, systems, and computer program products for generic process modeling. One method includes identifying a business process for execution, the business process defined by one or more process steps, identifying a process routing table associated with the identified business process, at least a portion of the process routing table including one or more entries defining a set of business process rules for the identified business process, identifying a particular entry in the process routing table associated with a current state of the identified business process; and performing at least one action defined by the identified particular entry in the process routing table. In some instances, at least one entry in the process routing table is associated with one of a plurality of process patterns, with each process pattern comprising a reusable, predefined operation.

    摘要翻译： 本公开描述了用于通用过程建模的方法，系统和计算机程序产品。 一种方法包括识别用于执行的业务流程，由一个或多个流程步骤定义的业务流程，识别与所识别的业务流程相关联的流程路由表，流程路由表的至少一部分包括定义集合的一个或多个条目 识别所识别的业务流程的业务流程规则，识别与所识别的业务流程的当前状态相关联的流程路由表中的特定条目; 以及执行由所述识别的特定条目在所述进程路由表中定义的至少一个动作。 在一些情况下，过程路由表中的至少一个条目与多个过程模式中的一个相关联，其中每个过程模式包括可重用的预定义操作。

    Financial services data model
    8.
    发明申请
    Financial services data model 有权
    金融服务数据模型

    公开(公告)号：US20070226093A1

    公开(公告)日：2007-09-27

    申请号：US10434533

    申请日：2003-05-08

    申请人： Cynthia Chan ,  Chiun-Feng Hsiao ,  Hwee Yeap ,  Yi Yang ,  Lindy Chan ,  Jing Gu ,  Caroline Muralitharan ,  Nardo Catahan ,  Blair Wheadon ,  Edward Chao ,  Hong Le Yuan

    发明人： Cynthia Chan ,  Chiun-Feng Hsiao ,  Hwee Yeap ,  Yi Yang ,  Lindy Chan ,  Jing Gu ,  Caroline Muralitharan ,  Nardo Catahan ,  Blair Wheadon ,  Edward Chao ,  Hong Le Yuan

    IPC分类号： G06Q40/00

    CPC分类号： G06Q40/00 ,  G06Q40/02

    摘要： A data model that allows for relationships between entities, also referred to as parties, to be modeled as attributes of an entity and for customization of the data model in a manner that facilitates upgrading of the data model. In some embodiments, the data model may facilitate creation and processing of financial applications. Using the data model, received application data can be stored in a financial application record, including data relating to a party's financial statements. In some embodiments, the data model may facilitate management of financial account data for multiple accounts. In some embodiments the data model may facilitate management of credit information, such as credit information collected by credit bureaus.

    摘要翻译： 允许将实体（也称为方）之间的关系建模为实体的属性并以促进数据模型升级的方式定制数据模型的数据模型。 在一些实施例中，数据模型可以促进金融应用的创建和处理。 使用数据模型，收到的应用数据可以存储在金融应用程序记录中，包括与一方的财务报表有关的数据。 在一些实施例中，数据模型可以促进对多个账户的金融账户数据的管理。 在一些实施例中，数据模型可以促进信用信息的管理，例如由信用局收集的信用信息。

    Easy process modeling platform
    9.
    发明授权
    Easy process modeling platform 有权
    简单的流程建模平台

    公开(公告)号：US08762187B2

    公开(公告)日：2014-06-24

    申请号：US13293965

    申请日：2011-11-10

    申请人： Jing Gu ,  Dong Wang ,  Yang Wang

    发明人： Jing Gu ,  Dong Wang ,  Yang Wang

    IPC分类号： G06Q10/00

    CPC分类号： G06Q10/0633 ,  G06Q10/06

    摘要： The present disclosure describes methods, systems, and computer program products for generic process modeling. One method includes identifying a business process for execution, the business process defined by one or more process steps, identifying a process routing table associated with the identified business process, at least a portion of the process routing table including one or more entries defining a set of business process rules for the identified business process, identifying a particular entry in the process routing table associated with a current state of the identified business process; and performing at least one action defined by the identified particular entry in the process routing table. In some instances, at least one entry in the process routing table is associated with one of a plurality of process patterns, with each process pattern comprising a reusable, predefined operation.

    摘要翻译： 本公开描述了用于通用过程建模的方法，系统和计算机程序产品。 一种方法包括识别用于执行的业务流程，由一个或多个流程步骤定义的业务流程，识别与所识别的业务流程相关联的流程路由表，流程路由表的至少一部分包括定义集合的一个或多个条目 识别所识别的业务流程的业务流程规则，识别与所识别的业务流程的当前状态相关联的流程路由表中的特定条目; 以及执行由所述识别的特定条目在所述进程路由表中定义的至少一个动作。 在一些情况下，过程路由表中的至少一个条目与多个过程模式中的一个相关联，其中每个过程模式包括可重用的预定义操作。