公开(公告)号：US06415403B1

公开(公告)日：2002-07-02

申请号：US09334569

申请日：1999-06-21

申请人： Jing-Reng Huang ,  Chih-Tsun Huang ,  Chi-Feng Wu ,  Cheng-Wen Wu

发明人： Jing-Reng Huang ,  Chih-Tsun Huang ,  Chi-Feng Wu ,  Cheng-Wen Wu

IPC分类号： G01R3128

CPC分类号： G11C29/16 ,  G01R31/3185 ,  G11C11/401

摘要： In the present invention a built in self test (BIST) for an embedded memory is described. The BIST can be used at higher levels of assembly and for commodity memories to perform functional and AC memory tests. A BIST controller comprising a finite state machine is used to step through a test sequence and control a sequence controller. The sequence controller provides data and timing sequences to the embedded memory to provide page mode and non-page mode tests along with a refresh test. The BIST logic is scan tested prior to performing the built in self test and accommodations for normal memory refresh is made throughout the testing. The BIST also accommodates a burn-in test where unique burn-in test sequences can be applied.

摘要翻译： 在本发明中，描述了嵌入式存储器的内置自检（BIST）。 BIST可以用于更高级别的装配和商品存储器，以执行功能和AC记忆测试。 使用包括有限状态机的BIST控制器来逐步测试序列并控制序列控制器。 序列控制器为嵌入式存储器提供数据和时序，以提供页面模式和非页面模式测试以及刷新测试。 BIST逻辑在执行内置自检之前进行扫描测试，并在整个测试过程中进行正常的内存刷新。 BIST还适用于可以应用独特的老化测试序列的老化测试。

公开(公告)号：US06934900B1

公开(公告)日：2005-08-23

申请号：US09887783

申请日：2001-06-25

申请人： Chuang Cheng ,  Chih-Tsun Huang ,  Jing-Reng Huang ,  Cheng-Wen Wu

发明人： Chuang Cheng ,  Chih-Tsun Huang ,  Jing-Reng Huang ,  Cheng-Wen Wu

IPC分类号： G01R31/28 ,  G01R31/3181 ,  G06F17/50 ,  G11C29/00 ,  G11C29/56

CPC分类号： G11C29/56004 ,  G01R31/31813 ,  G11C29/56

摘要： A test pattern generation and comparison circuit creates test pattern stimulus signals for and evaluates response signals from logic or memory such as random access memory (RAM). It utilizes both parallel and serial interfaces to the logic/memory under test. The test pattern generation and comparison circuit further provides a method for testing logic and memory utilizing built-in self test (BIST) techniques. The method uses a programmable logic/memory commands which are translated into physical logic signals and timings for the logic or memory under test. The results of the test pattern generated and applied to the logic or memory are compared to expected results. The result of the comparison is a pass/fail designation. In addition, the comparison of the expected test results with the actual test results provides information on the exact location of the failure. Also, since the test pattern generation and comparison circuit architecture is compatible with hardware description languages such as Verilog HDL or VHDL, the test pattern generation and comparison circuit can be automatically generated with a silicon compiler.

摘要翻译： 测试模式生成和比较电路为诸如随机存取存储器（RAM）等逻辑或存储器的响应信号创建测试模式激励信号并对其进行评估。 它将并行和串行接口连接到被测逻辑/内存。 测试图形生成和比较电路还提供了一种利用内置自检（BIST）技术来测试逻辑和存储器的方法。 该方法使用可编程逻辑/存储器命令，这些命令被转换为被测逻辑或存储器的物理逻辑信号和定时。 将生成并应用于逻辑或存储器的测试模式的结果与预期结果进行比较。 比较结果是通过/失败指定。 此外，预期测试结果与实际测试结果的比较提供了有关故障确切位置的信息。 此外，由于测试模式生成和比较电路架构与诸如Verilog HDL或VHDL的硬件描述语言兼容，所以测试模式生成和比较电路可以用硅编译器自动生成。

公开(公告)号：US07065689B2

公开(公告)日：2006-06-20

申请号：US10602377

申请日：2003-06-24

申请人： Sau-Kwo Chiu ,  Jen-Chieh Yeh ,  Kuo-Liang Cheng ,  Chih-Tsun Huang ,  Cheng-Wen Wu

发明人： Sau-Kwo Chiu ,  Jen-Chieh Yeh ,  Kuo-Liang Cheng ,  Chih-Tsun Huang ,  Cheng-Wen Wu

IPC分类号： G11C29/00 ,  G11C7/00 ,  G06F12/16

CPC分类号： G11C29/10 ,  G11C16/04

摘要： The present invention discloses a diagonal testing method for flash memories. The testing method regards the flash memory as several squares, and executes in the direction from top to bottom and from left to right. Each square is provided with a first diagonal in −45 degrees from the upper left to the lower right, and a second diagonal in +45 degrees from the lower left to the upper right. The present invention is to program the cells in the first diagonal or the second diagonal, and then read the cells except the first diagonal or the second diagonal; or, program the cells except the first diagonal or the second diagonal, and then read the cells in the first diagonal or the second diagonal so as to detect the disturb fault in the flash memories and normal memory fault models.

摘要翻译： 本发明公开了一种闪存的对角线测试方法。 测试方法将闪存存储为几个方格，并从上到下，从左到右的方向执行。 每个正方形设有从左上到右下的-45度的第一个对角线，以及从左下到右上的+45度的第二个对角线。 本发明是对第一对角线或第二对角线中的单元进行编程，然后读取第一对角线或第二对角线以外的单元; 或者，对第一对角线或第二对角线以外的单元进行编程，然后读取第一对角线或第二对角线中的单元，以便检测闪速存储器和正常存储器故障模型中的干扰故障。

公开(公告)号：US20060252375A1

公开(公告)日：2006-11-09

申请号：US11203380

申请日：2005-08-12

申请人： Cheng-Wen Wu ,  Chih-Tsun Huang ,  Yu-Tsao Hsing

发明人： Cheng-Wen Wu ,  Chih-Tsun Huang ,  Yu-Tsao Hsing

IPC分类号： H04B17/00

CPC分类号： H04B17/0085 ,  G01R31/3025 ,  G01R31/303

摘要： The present invention discloses a probing system for integrated circuit devices, which transmits testing data between an automatic test equipment (ATE) and an integrated circuit device. The ATE includes a first transceiving module, and the integrated circuit device includes a core circuit, a built-in self-test (BIST) circuit electrically connected to the core circuit, a controller configured to control the operation of the BIST circuit, and a second transceiving module configured to exchange testing data with the first transceiving module. Preferably, the integrated circuit device further includes a clock generator and a power regulator electrically connected to the second transceiving module, wherein the ATE transmits a radio frequency signal via the first transceiving module, and the second transceiving module receives the radio frequency signal to drive the power regulator to generate power for the integrated circuit device to initiate the BIST circuit.

摘要翻译： 本发明公开了一种用于在自动测试设备（ATE）和集成电路设备之间传输测试数据的集成电路设备的探测系统。 ATE包括第一收发模块，集成电路装置包括核心电路，电连接到核心电路的内置自测试（BIST）电路，被配置为控制BIST电路的操作的控制器，以及 第二收发模块被配置为与第一收发模块交换测试数据。 优选地，集成电路装置还包括时钟发生器和电连接到第二收发模块的功率调节器，其中ATE经由第一收发模块发送射频信号，第二收发模块接收射频信号以驱动 电源调节器为集成电路器件产生电源以启动BIST电路。

公开(公告)号：US07904768B2

公开(公告)日：2011-03-08

申请号：US12114768

申请日：2008-05-03

申请人： Cheng-Wen Wu ,  Chih-Tsun Huang ,  Yu-Tsao Hsing

发明人： Cheng-Wen Wu ,  Chih-Tsun Huang ,  Yu-Tsao Hsing

IPC分类号： G01R31/28

CPC分类号： G01R31/303 ,  G01R31/2886 ,  G01R31/3025 ,  H04B17/0085

摘要： A probing system for an integrated circuit device, which transmits a testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system includes a test head having a first transceiving module. There is a test station having a test unit coupled to the test head to perform a test operation. A communication module has a second transceiving module configured to exchange data with the first transceiving module in a wireless manner. There is an integrated circuit device having a core circuit being tested, and a test module having a self-test circuit coupled to the core circuit and the communication module for performing the core circuit self-testing.

摘要翻译： 公开了一种在自动测试设备（ATE）和集成电路设备之间传输测试数据/信号的集成电路设备的探测系统。 探测系统包括具有第一收发模块的测试头。 有一个测试站具有耦合到测试头的测试单元来执行测试操作。 通信模块具有被配置为以无线方式与第一收发模块交换数据的第二收发模块。 存在具有被测试的核心电路的集成电路器件，以及具有耦合到核心电路的自检电路和用于执行核心电路自检的通信模块的测试模块。

公开(公告)号：US20070232240A1

公开(公告)日：2007-10-04

申请号：US11761964

申请日：2007-06-12

申请人： Cheng-Wen Wu ,  Chih-Tsun Huang ,  Yu-Tsao Hsing

发明人： Cheng-Wen Wu ,  Chih-Tsun Huang ,  Yu-Tsao Hsing

IPC分类号： H04B1/38

CPC分类号： H04B17/0085 ,  G01R31/3025 ,  G01R31/303

摘要： The present invention discloses a probing system for integrated circuit devices, which transmits testing data between an automatic test equipment (ATE) and an integrated circuit device. The ATE includes a first transceiving module, and the integrated circuit device includes a core circuit, a built-in self-test (BIST) circuit electrically connected to the core circuit, a controller configured to control the operation of the BIST circuit, and a second transceiving module configured to exchange testing data with the first transceiving module. Preferably, the integrated circuit device further includes a clock generator and a power regulator electrically connected to the second transceiving module, wherein the ATE transmits a radio frequency signal via the first transceiving module, and the second transceiving module receives the radio frequency signal to drive the power regulator to generate power for the integrated circuit device to initiate the BIST circuit.

摘要翻译： 本发明公开了一种用于在自动测试设备（ATE）和集成电路设备之间传输测试数据的集成电路设备的探测系统。 ATE包括第一收发模块，集成电路装置包括核心电路，电连接到核心电路的内置自测试（BIST）电路，被配置为控制BIST电路的操作的控制器，以及 第二收发模块被配置为与第一收发模块交换测试数据。 优选地，集成电路装置还包括时钟发生器和电连接到第二收发模块的功率调节器，其中ATE经由第一收发模块发送射频信号，第二收发模块接收射频信号以驱动 电源调节器为集成电路器件产生电源以启动BIST电路。

公开(公告)号：US07117409B2

公开(公告)日：2006-10-03

申请号：US10735298

申请日：2003-12-12

申请人： Cheng-Wen Wu ,  Chih-Tsun Huang ,  Chih-Wea Wang ,  Kao-Liang Cheng

发明人： Cheng-Wen Wu ,  Chih-Tsun Huang ,  Chih-Wea Wang ,  Kao-Liang Cheng

IPC分类号： G11C20/10 ,  G11C7/22

CPC分类号： G11C29/025 ,  G11C8/16 ,  G11C29/02 ,  G11C29/50012

摘要： In a method of testing a multi-port memory in accordance with a test pattern, test clock signals having the same test clock frequency but with different delay periods introduced therein are generated for controlling memory access through the different access ports of the memory. Consecutive memory operations of a test element of the test pattern are then conducted in a folded sequence upon a memory cell through the different access ports in accordance with the test clock signals such that the memory operations are completed within the same test clock cycle of the test element.

摘要翻译： 在根据测试模式测试多端口存储器的方法中，生成具有相同测试时钟频率但具有不同延迟周期的测试时钟信号，用于控制通过存储器的不同访问端口的存储器访问。 测试模式的测试元件的连续存储器操作然后按照测试时钟信号通过不同的存取端口以折叠的顺序进行到存储器单元上，使得存储器操作在测试的相同测试时钟周期内完成 元件。