公开(公告)号：US06278964B1

公开(公告)日：2001-08-21

申请号：US09087413

申请日：1998-05-29

申请人： Jingkun Fang ,  Hirokazu Yonezawa ,  Lifeng Wu ,  Yoshiyuki Kawakami ,  Nobufusa Iwanishi ,  Alvin I-Hsien Chen ,  Norio Koike ,  Ping Chen ,  Chune-Sin Yeh ,  Zhihong Liu

发明人： Jingkun Fang ,  Hirokazu Yonezawa ,  Lifeng Wu ,  Yoshiyuki Kawakami ,  Nobufusa Iwanishi ,  Alvin I-Hsien Chen ,  Norio Koike ,  Ping Chen ,  Chune-Sin Yeh ,  Zhihong Liu

IPC分类号： G06F1126

CPC分类号： G01R31/318357 ,  G01R31/318328 ,  G06F17/5022

摘要： An approach for simulating hot carrier effects in an integrated circuit (IC) at the circuit level includes generating a hot carrier library of delay data for each cell in the IC, using the hot carrier library data to generate a set of scaled timing data for the IC and using the scaled timing data with a IC performance simulator to simulate the IC operation. The scaled timing data is based upon the cell delay data and time-based switching activity of each cell in the IC.

摘要翻译： 用于在电路级模拟集成电路（IC）中的热载流子效应的方法包括使用热载体库数据产生一组缩放的定时数据，以生成针对IC卡中的每个单元的延迟数据的热载体库 IC，并使用IC性能仿真器对缩放的时序数据进行模拟，以模拟IC的工作。 缩放的定时数据基于IC中每个单元的单元延迟数据和基于时间的切换活动。

公开(公告)号：US20090299716A1

公开(公告)日：2009-12-03

申请号：US12486191

申请日：2009-06-17

申请人： Zhihong Liu ,  Lifeng Wu ,  Jeong Y. Choi ,  Ping Chen ,  Alvin I. Chen ,  Gang Zhang

发明人： Zhihong Liu ,  Lifeng Wu ,  Jeong Y. Choi ,  Ping Chen ,  Alvin I. Chen ,  Gang Zhang

IPC分类号： G06F17/50 ,  G01R31/26

CPC分类号： G06F17/5036 ,  G01R31/2848 ,  G06F2217/78

摘要： The present invention is directed to a number of improvements in methods for hot-carrier device degradation modeling and extraction. Several improvements are presented for the improvement of building device degradation models, including allowing the user to select a device parameter used to build the device degradation model independent of the device parameter selected. The user can also select the functional relation between stress time and degradation level. To further improve accuracy, multiple acceleration parameters can be used to account for different regions of the degradation process. Analytical functions may be used to represent aged device model parameters, either directly or by fitting measured device parameters versus device age values, allowing devices with different age values to share the same device model. The concept of binning is extended to include device degradation. In addition to a binning based on device width and length, age is added. In an exemplary embodiment, only devices with minimum channel length have degraded models constructed. The present invention also allows the degradation of one device parameter to be determined based on an age value derived from another parameter. In yet another aspect, a degraded device is modeled as a fresh device with a voltage source connected to a terminal.

摘要翻译： 本发明涉及用于热载体装置降解建模和提取的方法的许多改进。 提出了改进建筑设备劣化模型的几个改进，包括允许用户选择用于构建设备退化模型的设备参数，而不依赖于所选择的设备参数。 用户还可以选择应力时间与劣化水平之间的功能关系。 为了进一步提高精度，可以使用多个加速参数来解释退化过程的不同区域。 分析功能可以直接表示老化的设备模型参数，也可以通过拟合测量的设备参数与设备寿命值进行比较，从而允许具有不同年龄值的设备共享相同的设备型号。 分箱的概念被扩展到包括设备退化。 除了基于设备宽度和长度的分类，还添加了年龄。 在示例性实施例中，只有具有最小信道长度的设备具有构造的退化模型。 本发明还允许基于从另一参数导出的年龄值来确定一个设备参数的劣化。 在另一方面，劣化设备被建模为具有连接到终端的电压源的新设备。

公开(公告)号：US07567891B1

公开(公告)日：2009-07-28

申请号：US09969185

申请日：2001-09-27

申请人： Zhihong Liu ,  Lifeng Wu ,  Jeong Y. Choi ,  Ping Chen ,  Alvin I. Chen ,  Gang Zhang

发明人： Zhihong Liu ,  Lifeng Wu ,  Jeong Y. Choi ,  Ping Chen ,  Alvin I. Chen ,  Gang Zhang

IPC分类号： G06F7/60 ,  G06F17/50 ,  G06F9/45 ,  G01R15/00 ,  G01R27/28 ,  G01R27/26 ,  H03K19/20 ,  H03K19/094

CPC分类号： G06F17/5036 ,  G01R31/2848 ,  G06F2217/78

摘要： The present invention is directed to a number of improvements in methods for hot-carrier device degradation modeling and extraction. Several improvements are presented for the improvement of building device degradation models, including allowing the user to select a device parameter used to build the device degradation model independent of the device parameter selected. The user can also select the functional relation between stress time and degradation level. To further improve accuracy, multiple acceleration parameters can be used to account for different regions of the degradation process. Analytical functions may be used to represent aged device model parameters, either directly or by fitting measured device parameters versus device age values, allowing devices with different age values to share the same device model. The concept of binning is extended to include device degradation. In addition to a binning based on device width and length, age is added. In an exemplary embodiment, only devices with minimum channel length have degraded models constructed. The present invention also allows the degradation of one device parameter to be determined based on an age value derived from another parameter. In yet another aspect, a degraded device is modeled as a fresh device with a voltage source connected to a terminal.

摘要翻译： 本发明涉及用于热载体装置降解建模和提取的方法的许多改进。 提出了改进建筑设备劣化模型的几个改进，包括允许用户选择用于构建设备退化模型的设备参数，而不依赖于所选择的设备参数。 用户还可以选择应力时间与劣化水平之间的功能关系。 为了进一步提高精度，可以使用多个加速参数来解释退化过程的不同区域。 分析功能可以直接表示老化的设备模型参数，也可以通过拟合测量的设备参数与设备寿命值进行比较，从而允许具有不同年龄值的设备共享相同的设备型号。 分箱的概念被扩展到包括设备退化。 除了基于设备宽度和长度的分类，还添加了年龄。 在示例性实施例中，只有具有最小信道长度的设备具有构造的退化模型。 本发明还允许基于从另一参数导出的年龄值来确定一个设备参数的劣化。 在另一方面，劣化设备被建模为具有连接到终端的电压源的新设备。

公开(公告)号：US06560755B1

公开(公告)日：2003-05-06

申请号：US09648396

申请日：2000-08-24

申请人： Xisheng Zhang ,  James Chieh-Tsung Chen ,  Zhihong Liu ,  Jushan Xie ,  Xucheng Pang ,  Jingkun Fang

发明人： Xisheng Zhang ,  James Chieh-Tsung Chen ,  Zhihong Liu ,  Jushan Xie ,  Xucheng Pang ,  Jingkun Fang

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： An exemplary method for simulating the effect of mismatch in design flows comprises receiving measured data, receiving an original model, extracting a mismatch model based on the measured data and the original model, attaching the mismatch model to the netlist to obtain a modified netlist, and simulating an effect of mismatch based on the modified netlist. In one embodiment, the extracting of a mismatch model includes selecting a set of model parameters, generating a distribution of mismatch values for each of the model parameters, extracting a set of linking coefficients based on said mismatch values, and extracting said mismatch model based on said set of linking coefficients. In another embodiment, the attaching of the mismatch model to the netlist includes determining a number of layers in the netlist, generating a copy of a lower layer in the netlist, the copy including a reference to a mismatch model definition, generating a copy of a higher layer in the netlist, replacing a reference to the lower layer in the higher layer by a reference to the copy of the lower layer, and generating a new model definition.

摘要翻译： 用于模拟设计流程中的不匹配效应的示例性方法包括接收测量数据，接收原始模型，基于测量数据和原始模型提取失配模型，将不匹配模型附加到网表以获得修改的网表，以及 基于修改的网表模拟不匹配的影响。 在一个实施例中，提取失配模型包括选择一组模型参数，生成每个模型参数的失配值分布，基于所述失配值提取一组链接系数，以及基于 所述一组链接系数。 在另一个实施例中，将不匹配模型附加到网表包括确定网表中的层数，生成网表中较低层的副本，该副本包括对不匹配模型定义的引用，生成 网表中的较高层，通过对较低层的副本的引用替代对较高层中较低层的引用，并生成新的模型定义。

公开(公告)号：US20090119085A1

公开(公告)日：2009-05-07

申请号：US11935969

申请日：2007-11-06

申请人： Yutao Ma ,  Min-Chie Jeng ,  Bruce W. McGaughy ,  Lifeng Wu ,  Zhihong Liu

发明人： Yutao Ma ,  Min-Chie Jeng ,  Bruce W. McGaughy ,  Lifeng Wu ,  Zhihong Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Method and system are disclosed for modeling dynamic behavior of a transistor. The method includes representing static behavior of a transistor using a lookup table, selecting an instance of the transistor from the lookup table for modeling dynamic behavior of the transistor, computing a previous state of the instance using a non-quasi static analytical model, computing a variation in channel charge of the instance according to a rate of change in time, computing a current state of the instance using the previous state and the variation in channel charge, computing a modified terminal voltage that includes a dynamic voltage across a parasitic resistance at the terminal of the transistor according to the current state and previous state of the instance, and storing the modified terminal voltage in a memory device for modeling dynamic behavior of the transistor at the current state.

摘要翻译： 公开了用于建模晶体管的动态行为的方法和系统。 该方法包括使用查找表来表示晶体管的静态特性，从查找表中选择晶体管的实例以建模晶体管的动态行为，使用非准静态分析模型计算实例的先前状态，计算 根据时间变化率计算实例的信道电荷的变化，使用先前状态计算实例的当前状态和信道电荷的变化，计算修改的终端电压，该电压包括两端的寄生电阻两端的动态电压 根据当前状态和实例的先前状态，晶体管的端子，并将修改的端子电压存储在用于对当前状态下的晶体管的动态行为进行建模的存储器件中。

公开(公告)号：US07933747B2

公开(公告)日：2011-04-26

申请号：US11935969

申请日：2007-11-06

申请人： Yutao Ma ,  Min-Chie Jeng ,  Bruce W. McGaughy ,  Lifeng Wu ,  Zhihong Liu

发明人： Yutao Ma ,  Min-Chie Jeng ,  Bruce W. McGaughy ,  Lifeng Wu ,  Zhihong Liu

IPC分类号： G06F17/10

CPC分类号： G06F17/5036

摘要： Method and system are disclosed for modeling dynamic behavior of a transistor. The method includes representing static behavior of a transistor using a lookup table, selecting an instance of the transistor from the lookup table for modeling dynamic behavior of the transistor, computing a previous state of the instance using a non-quasi static analytical model, computing a variation in channel charge of the instance according to a rate of change in time, computing a current state of the instance using the previous state and the variation in channel charge, computing a modified terminal voltage that includes a dynamic voltage across a parasitic resistance at the terminal of the transistor according to the current state and previous state of the instance, and storing the modified terminal voltage in a memory device for modeling dynamic behavior of the transistor at the current state.

摘要翻译： 公开了用于建模晶体管的动态行为的方法和系统。 该方法包括使用查找表来表示晶体管的静态特性，从查找表中选择晶体管的实例以建模晶体管的动态行为，使用非准静态分析模型计算实例的先前状态，计算 根据时间变化率计算实例的信道电荷的变化，使用先前状态计算实例的当前状态和信道电荷的变化，计算修改的终端电压，该电压包括两端的寄生电阻两端的动态电压 根据当前状态和实例的先前状态，晶体管的端子，并将修改的端子电压存储在用于对当前状态下的晶体管的动态行为进行建模的存储器件中。

公开(公告)号：US07835890B2

公开(公告)日：2010-11-16

申请号：US11867554

申请日：2007-10-04

申请人： Lifeng Wu ,  Zhihong Liu ,  Alvin I. Chen ,  Jeong Y. Choi ,  Bruce W. McGaughy

发明人： Lifeng Wu ,  Zhihong Liu ,  Alvin I. Chen ,  Jeong Y. Choi ,  Bruce W. McGaughy

IPC分类号： G06F17/50 ,  G06F9/44

CPC分类号： G06F17/5036

摘要： The present invention is directed to a number of improvements in methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects. A plurality of different circuit stress times can be simulated within a single run. Different aging criteria may be used for different circuit blocks, circuit block types, devices, device models and device types. The user may specify the degradation of selected circuit blocks, circuit block types, devices, device models and device types independently of the simulation. Device degradation can be characterized in tables. Continuous degradation levels can be quantized. Techniques are also described for representing the aged device in the netlist as the fresh device augmented with a plurality of independent current sources connected between its terminals to mimic the effects of aging in the device. The use of device model cards with age parameters is also described. To further improve the circuit reliability simulation, a gradual or multi-step aging is used instead of the standard one step aging process. Many of these features can be embedded within the circuit simulator. A user data interface is also presented to implement these techniques and further allow users to enter their device models not presented in the simulator. For example, a proprietary model of, say, the substrate current in an NMOS could used be with a SPICE simulator employing a different model to simulate the aging of the circuit.

摘要翻译： 本发明涉及在老化电路中的可靠性模拟方法的许多改进，其操作已经通过热载波或其它效应而降级。 可以在单次运行中模拟多个不同的电路应力时间。 不同的老化标准可用于不同的电路块，电路块类型，器件，器件型号和器件类型。 用户可以独立于模拟来指定所选择的电路块，电路块类型，设备，设备模型和设备类型的劣化。 器件劣化可以在表中进行表征。 可以量化连续降解水平。 还描述了用于在网表中表示老化设备的技术，因为新设备通过连接在其终端之间的多个独立电流源来增强，以模拟设备中的老化的影响。 还描述了使用具有年龄参数的设备型号卡。 为了进一步提高电路可靠性仿真，采用逐步或多步老化代替标准的一步老化过程。 这些功能中的许多可以嵌入在电路仿真器中。 还呈现用户数据接口以实现这些技术，并且进一步允许用户输入其未在模拟器中呈现的设备模型。 例如，一个专有的模型，例如NMOS中的衬底电流可以用SPICE仿真器使用不同的模型来模拟电路的老化。

公开(公告)号：US20080027699A1

公开(公告)日：2008-01-31

申请号：US11867554

申请日：2007-10-04

申请人： Lifeng Wu ,  Zhihong Liu ,  Alvin Chen ,  Jeong Choi ,  Bruce McGaughy

发明人： Lifeng Wu ,  Zhihong Liu ,  Alvin Chen ,  Jeong Choi ,  Bruce McGaughy

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： The present invention is directed to a number of improvements in methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects. A plurality of different circuit stress times can be simulated within a single run. Different aging criteria may be used for different circuit blocks, circuit block types, devices, device models and device types. The user may specify the degradation of selected circuit blocks, circuit block types, devices, device models and device types independently of the simulation. Device degradation can be characterized in tables. Continuous degradation levels can be quantized. Techniques are also described for representing the aged device in the netlist as the fresh device augmented with a plurality of independent current sources connected between its terminals to mimic the effects of aging in the device. The use of device model cards with age parameters is also described. To further improve the circuit reliability simulation, a gradual or multi-step aging is used instead of the standard one step aging process. Many of these features can be embedded within the circuit simulator. A user data interface is also presented to implement these techniques and further allow users to enter their device models not presented in the simulator. For example, a proprietary model of, say, the substrate current in an NMOS could used be with a SPICE simulator employing a different model to simulate the aging of the circuit.

摘要翻译： 本发明涉及在老化电路中的可靠性模拟方法的许多改进，其操作已经通过热载波或其它效应而降级。 可以在单次运行中模拟多个不同的电路应力时间。 不同的老化标准可用于不同的电路块，电路块类型，器件，器件型号和器件类型。 用户可以独立于模拟来指定所选择的电路块，电路块类型，设备，设备模型和设备类型的劣化。 器件劣化可以在表中进行表征。 可以量化连续降解水平。 还描述了用于在网表中表示老化设备的技术，因为新设备通过连接在其终端之间的多个独立电流源来增强，以模拟设备中的老化的影响。 还描述了使用具有年龄参数的设备型号卡。 为了进一步提高电路可靠性仿真，采用逐步或多步老化代替标准的一步老化过程。 这些功能中的许多可以嵌入在电路仿真器中。 还呈现用户数据接口以实现这些技术，并且进一步允许用户输入其未在模拟器中呈现的设备模型。 例如，一个专有的模型，例如NMOS中的衬底电流可以用SPICE仿真器使用不同的模型来模拟电路的老化。

公开(公告)号：US07292968B2

公开(公告)日：2007-11-06

申请号：US09832933

申请日：2001-04-11

申请人： Lifeng Wu ,  Zhihong Liu ,  Alvin I. Chen ,  Jeong Y. Choi ,  Bruce W. McGaughy

发明人： Lifeng Wu ,  Zhihong Liu ,  Alvin I. Chen ,  Jeong Y. Choi ,  Bruce W. McGaughy

IPC分类号： G06F17/50 ,  G06F9/44

CPC分类号： G06F17/5036

摘要： The present invention is directed to a number of improvements in methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects. A plurality of different circuit stress times can be simulated within a single run. Different aging criteria may be used for different circuit blocks, circuit block types, devices, device models and device types. The user may specify the degradation of selected circuit blocks, circuit block types, devices, device models and device types independently of the simulation. Device degradation can be characterized in tables. Continuous degradation levels can be quantized. Techniques are also described for representing the aged device in the netlist as the fresh device augmented with a plurality of independent current sources connected between its terminals to mimic the effects of aging in the device. The use of device model cards with age parameters is also described. To further improve the circuit reliability simulation, a gradual or multi-step aging is used instead of the standard one step aging process. Many of these features can be embedded within the circuit simulator. A user data interface is also presented to implement these techniques and further allow users to enter their device models not presented in the simulator. For example, a proprietary model of, say, the substrate current in an NMOS could used be with a SPICE simulator employing a different model to simulate the aging of the circuit.

摘要翻译： 本发明涉及在老化电路中的可靠性模拟方法的许多改进，其操作已经通过热载波或其它效应而降级。 可以在单次运行中模拟多个不同的电路应力时间。 不同的老化标准可用于不同的电路块，电路块类型，器件，器件型号和器件类型。 用户可以独立于模拟来指定所选择的电路块，电路块类型，设备，设备模型和设备类型的劣化。 器件劣化可以在表中进行表征。 可以量化连续降解水平。 还描述了用于在网表中表示老化设备的技术，因为新设备通过连接在其终端之间的多个独立电流源来增强，以模拟设备中的老化的影响。 还描述了使用具有年龄参数的设备型号卡。 为了进一步提高电路可靠性仿真，采用逐步或多步老化代替标准的一步老化过程。 这些功能中的许多可以嵌入在电路仿真器中。 还呈现用户数据接口以实现这些技术，并且进一步允许用户输入其未在模拟器中呈现的设备模型。 例如，一个专有的模型，例如NMOS中的衬底电流可以用SPICE仿真器使用不同的模型来模拟电路的老化。

公开(公告)号：US07263477B2

公开(公告)日：2007-08-28

申请号：US10457945

申请日：2003-06-09

申请人： Ping Chen ,  Zhihong Liu

发明人： Ping Chen ,  Zhihong Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： The present invention includes a method for modeling devices having different geometries, in which a range of interest for device geometrical variations is divided into a plurality of subregions each corresponding to a subrange of device geometrical variations. The plurality of subregions include a first type of subregions and a second type of subregions. The first or second type of subregions include one or more subregions. A regional global model is generated for each of the first type of subregions and a binning model is generated for each of the second type of subregions. The regional global model for a subregion uses one set of model parameters to comprehend the subrange of device geometrical variations corresponding to the G-type subregion. The binning model for a subregion includes binning parameters to provide continuity of the model parameters when device geometry varies across two different subregions.

摘要翻译： 本发明包括一种用于建模具有不同几何形状的装置的方法，其中将装置几何变化的感兴趣的范围分成多个子区域，每个子区域对应于装置几何变化的子范围。 多个子区域包括第一类型的子区域和第二类型的子区域。 第一或第二类型的子区域包括一个或多个子区域。 为每个第一类型的子区域生成区域全局模型，并且为第二类型的子区域中的每一个生成分类模型。 一个次区域的区域全球模型使用一组模型参数来理解与G型子区域相对应的设备几何变化的子范围。 一个子区域的分箱模型包括分箱参数，以便在两个不同子区域之间设备几何变化时提供模型参数的连续性。