公开(公告)号：US06278964B1

公开(公告)日：2001-08-21

申请号：US09087413

申请日：1998-05-29

申请人： Jingkun Fang ,  Hirokazu Yonezawa ,  Lifeng Wu ,  Yoshiyuki Kawakami ,  Nobufusa Iwanishi ,  Alvin I-Hsien Chen ,  Norio Koike ,  Ping Chen ,  Chune-Sin Yeh ,  Zhihong Liu

发明人： Jingkun Fang ,  Hirokazu Yonezawa ,  Lifeng Wu ,  Yoshiyuki Kawakami ,  Nobufusa Iwanishi ,  Alvin I-Hsien Chen ,  Norio Koike ,  Ping Chen ,  Chune-Sin Yeh ,  Zhihong Liu

IPC分类号： G06F1126

CPC分类号： G01R31/318357 ,  G01R31/318328 ,  G06F17/5022

摘要： An approach for simulating hot carrier effects in an integrated circuit (IC) at the circuit level includes generating a hot carrier library of delay data for each cell in the IC, using the hot carrier library data to generate a set of scaled timing data for the IC and using the scaled timing data with a IC performance simulator to simulate the IC operation. The scaled timing data is based upon the cell delay data and time-based switching activity of each cell in the IC.

摘要翻译： 用于在电路级模拟集成电路（IC）中的热载流子效应的方法包括使用热载体库数据产生一组缩放的定时数据，以生成针对IC卡中的每个单元的延迟数据的热载体库 IC，并使用IC性能仿真器对缩放的时序数据进行模拟，以模拟IC的工作。 缩放的定时数据基于IC中每个单元的单元延迟数据和基于时间的切换活动。

公开(公告)号：US06795802B2

公开(公告)日：2004-09-21

申请号：US09810518

申请日：2001-03-19

申请人： Hirokazu Yonezawa ,  Yoshiyuki Kawakami ,  Nobufusa Iwanishi

发明人： Hirokazu Yonezawa ,  Yoshiyuki Kawakami ,  Nobufusa Iwanishi

IPC分类号： G06F1710

CPC分类号： G01R31/318371 ,  G01R31/287 ,  G01R31/318342

摘要： The present invention makes it possible to obtain an aging deterioration margin amount including an allowance for aging deterioration in a simplified manner. Moreover, in order to allow an appropriate inspection taking aging deterioration into account, a delay deterioration rate predicting part 101 outputs signal path delay information before deterioration 302 and signal path delay deterioration rate information 303 for each signal path, based on LSI design information 301. A delay vs. delay deterioration rate analyzing part 102 outputs delay vs. delay deterioration rate relationship information 304 showing the correlation between the delay and the delay deterioration rate based on the information. A delay deterioration rate extracting part 103 extracts a delay deterioration rate of a predetermined signal path and outputs it as delay deterioration margin 305. A delay deterioration margin amount calculating part 104 calculates a delay deterioration margin amount by using the delay deterioration margin 305 as a derating factor G. Furthermore, a inspection operation frequency calculating part 105 calculates an operation frequency for inspection using the delay deterioration margin 305 as a derating factor G.

摘要翻译： 本发明使得可以简化地获得包括老化劣化余地的老化退化裕度量。 此外，为了考虑老化劣化的适当检查，延迟劣化率预测部101基于LSI设计信息301，对各信号路径输出恶化前的信号路径延迟信息302和信号路径延迟劣化率信息303。 延迟与延迟劣化率分析部分102基于该信息输出延迟与延迟退化率关系信息304，其显示延迟和延迟退化率之间的相关性。 延迟劣化率提取部分103提取预定信号路径的延迟劣化率，并将其作为延迟劣化边缘305输出。延迟劣化边际量计算部分104通过使用延迟劣化边缘305作为降额来计算延迟劣化边际量 另外，检查动作频率计算部105使用延迟劣化余量305作为降额因子G来计算检查用的操作频率。

公开(公告)号：US06498515B2

公开(公告)日：2002-12-24

申请号：US10142969

申请日：2002-05-13

申请人： Yoshiyuki Kawakami ,  Nobufusa Iwanishi

发明人： Yoshiyuki Kawakami ,  Nobufusa Iwanishi

IPC分类号： H03K1920

CPC分类号： H03K19/00323 ,  G06F17/505

摘要： A logical design method for a semiconductor integrated circuit includes the steps of: a) generating a circuit at a logical level so as to meet given functions and specifications; b) extracting a critical path, which will cause the longest delay, from the circuit generated in the step a); c) counting how many times a path leading from each input terminal to an output terminal in every logic cell of the circuit has operated; d) calculating a degradation rate associated with the path leading from each said input terminal to the output terminal in each said logic cell on the critical path by reference to the number of times of operation obtained in the step c); and e) exchanging a connection to one of the input terminals of each said logic cell, which terminal is associated with the critical path, with a connection to another one of the input terminals of the logic cell, which terminal is associated with another path corresponding to a lower degradation rate than that of the critical path, by reference to the degradation rates obtained in the step d).

摘要翻译： 一种用于半导体集成电路的逻辑设计方法包括以下步骤：a）产生逻辑电平的电路以满足给定的功能和规格; b）提取从步骤a）中产生的电路产生最长延迟的关键路径; c）计算从电路的每个逻辑单元中的每个输入端子到输出端子的路径的操作次数; d）通过参考步骤c）中获得的操作次数，计算在关键路径上的每个所述逻辑单元中从每个所述输入端子到输出端子的路径相关联的退化率; 以及e）通过与逻辑单元的另一个输入端子的连接来与每个所述逻辑单元的哪个终端与关键路径相关联的输入终端之一交换连接，该终端与另一路径相关联 通过参考在步骤d）中获得的降解速率降低到关键路径的降解速率。

公开(公告)号：US06396307B1

公开(公告)日：2002-05-28

申请号：US09573568

申请日：2000-05-19

申请人： Yoshiyuki Kawakami ,  Nobufusa Iwanishi

发明人： Yoshiyuki Kawakami ,  Nobufusa Iwanishi

IPC分类号： H03K1920

CPC分类号： H03K19/00323 ,  G06F17/505

摘要： A logical design method for a semiconductor integrated circuit includes the steps of: a) generating a circuit at a logical level so as to meet given functions and specifications; b) extracting a critical path, which will cause the longest delay, from the circuit generated in the step a); c) counting how many times a path leading from each input terminal to an output terminal in every logic cell of the circuit has operated; d) calculating a degradation rate associated with the path leading from each said input terminal to the output terminal in each said logic cell on the critical path by reference to the number of times of operation obtained in the step c); and e) exchanging a connection to one of the input terminals of each said logic cell, which terminal is associated with the critical path, with a connection to another one of the input terminals of the logic cell, which terminal is associated with another path corresponding to a lower degradation rate than that of the critical path, by reference to the degradation rates obtained in the step d).

公开(公告)号：US6047247A

公开(公告)日：2000-04-04

申请号：US986321

申请日：1997-12-05

申请人： Nobufusa Iwanishi ,  Yoshiyuki Kawakami

发明人： Nobufusa Iwanishi ,  Yoshiyuki Kawakami

IPC分类号： G06F11/00 ,  G06F11/26

CPC分类号： G06F11/008

摘要： There is provided a hot-carrier-delay-degradation estimation method of estimating, based on the actual operation of an LSI, deterioration in reliability thereof due to the influence of hot carriers. At a delay calculation step, there are calculated, for the cells of an LSI serving as the object of timing verification, delays, input slew and output load capacitances based on circuit information and a delay library containing delay parameters. At a delay degradation library generation step, there is generated a delay degradation library containing delay parameters at the time when the LSI has operated for a predetermined period of time. This delay degradation library is generated (i) based on the delay library and delay degradation parameters in which changes in delay of the cells due to the influence of hot carriers are expressed in terms of changes in delay parameter accompanied by the numbers of operation times of the cells and (ii) with the use of the estimated numbers of operation times, input waveform inclinations and output load capacitances of the cells. By repeating these two steps the predetermined number of repetition times, there are obtained delays of the cells at the time when the LSI has operated for a period of time equivalent to the product of the predetermined period of time and the number of repetition times.

摘要翻译： 提供了一种基于LSI的实际操作来估计由于热载体的影响导致的可靠性劣化的热载波延迟劣化估计方法。 在延迟计算步骤中，对于作为定时验证对象的LSI的单元，基于电路信息和包含延迟参数的延迟库来计算延迟，输入转换和输出负载电容。 在延迟劣化库生成步骤中，产生延迟劣化库，该延迟劣化库在LSI已经操作预定时间段时包含延迟参数。 基于延迟库和延迟劣化参数产生延迟退化库（i），其中由于热载波的影响导致的单元的延迟变化以延迟参数的变化表示，伴随着操作次数 （ii）使用估计的操作次数，单元的输入波形倾斜度和输出负载电容。 通过重复这两个步骤预定次数的重复次数，在LSI已经操作了等于预定时间段和重复次数的乘积的时间段时，获得了单元的延迟。

公开(公告)号：US20070143723A1

公开(公告)日：2007-06-21

申请号：US11642725

申请日：2006-12-21

申请人： Yoshiyuki Kawakami

发明人： Yoshiyuki Kawakami

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： In timing verification considering process variations in the fabrication of semiconductor integrated circuits, parasitic element extraction results are obtained with high accuracy by considering variations in interconnect configuration occurring randomly inside LSI to perform timing verification of worst-case or best-case simulation. For example, a plurality of capacitance libraries are prepared according to process variations in the fabrication of semiconductor integrated circuits, such as variations in interconnect width, interconnect film thickness and interlayer film thickness, and one is selected among these capacitance libraries properly according to the target layout. In this way, parasitic element extraction results for worst-case or best-case simulation can be obtained with high accuracy for the target layout.

摘要翻译： 考虑到半导体集成电路制造中的工艺变化的定时验证，通过考虑在LSI内部随机发生的互连配置的变化来实现最坏情况或最佳情况模拟的定时验证，从而以高精度获得寄生元件提取结果。 例如，根据半导体集成电路的制造中的工艺变化制备多个电容库，例如互连宽度，互连膜厚度和层间膜厚度的变化，并且根据目标适当选择这些电容库 布局。 以这种方式，可以以目标布局的高精度获得最坏情况或最佳情况下的寄生元件提取结果。

公开(公告)号：US07915306B2

公开(公告)日：2011-03-29

申请号：US10657910

申请日：2003-09-09

申请人： Kenichi Chiba ,  Hong Du ,  Yoshihito Eguchi ,  Masanori Fujita ,  Masaki Goto ,  Fabian Gusovsky ,  Jean-Christophe Harmange ,  Atsushi Inoue ,  Megumi Kawada ,  Takatoshi Kawai ,  Yoshiyuki Kawakami ,  Akifumi Kimura ,  Makoto Kotake ,  Yoshikazu Kuboi ,  Tomohiro Matsushima ,  Yoshiharu Mizui ,  Kenzo Muramoto ,  Hideki Sakurai ,  Yong-Chun Shen ,  Hiroshi Shirota ,  Mark Spyvee ,  Isao Tanaka ,  John (Yuan) Wang ,  Ray Wood ,  Satoshi Yamamoto ,  Naoki Yoneda

发明人： Kenichi Chiba ,  Hong Du ,  Yoshihito Eguchi ,  Masanori Fujita ,  Masaki Goto ,  Fabian Gusovsky ,  Jean-Christophe Harmange ,  Atsushi Inoue ,  Megumi Kawada ,  Takatoshi Kawai ,  Yoshiyuki Kawakami ,  Akifumi Kimura ,  Makoto Kotake ,  Yoshikazu Kuboi ,  Tomohiro Matsushima ,  Yoshiharu Mizui ,  Kenzo Muramoto ,  Hideki Sakurai ,  Yong-Chun Shen ,  Hiroshi Shirota ,  Mark Spyvee ,  Isao Tanaka ,  John (Yuan) Wang ,  Ray Wood ,  Satoshi Yamamoto ,  Naoki Yoneda

IPC分类号： A61K31/335

CPC分类号： C07D493/04 ,  C07D313/00

摘要： The present invention provides compositions comprising compounds having formula (I): and additionally provides methods for the use thereof in the treatment of various disorders including inflammatory or autoimmune disorders, and disorders involving malignancy or increased angiogenesis, wherein R1-R11, X, Y, Z, and n are as defined herein. In certain embodiments, the compositions are for systemic (e.g., oral) administration. In certain embodiments, methods for the treatment of various disorders including inflammatory or autoimmune disorders comprise systemically (e.g., orally) administering to a subject in need thereof a therapeutically effective amount of a compound of formula (I).

摘要翻译： 本发明提供了包含具有式（I）的化合物的组合物：另外提供了其用于治疗各种疾病（包括炎性或自身免疫性疾病）以及涉及恶性肿瘤或增加血管发生的疾病的方法，其中R1-R11，X，Y， Z和n如本文所定义。 在某些实施方案中，组合物用于全身（例如口服）给药。 在某些实施方案中，用于治疗各种疾病（包括炎性或自身免疫性疾病）的方法包括全身（例如，口服）向有需要的受试者施用治疗有效量的式（I）化合物。

公开(公告)号：US07541625B2

公开(公告)日：2009-06-02

申请号：US11883539

申请日：2006-03-03

申请人： Yoshiyuki Kawakami

发明人： Yoshiyuki Kawakami

IPC分类号： H01L21/768

CPC分类号： H01L27/0203 ,  H01L21/31053 ,  H01L21/7684 ,  H01L23/5222 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： When dummy patterns are arranged to planarize LSI layout patterns, a plurality of dummy patterns 1 are arranged in a wiring layer in which signal wiring patterns 2 are formed, so as to be inclined at an angle of generally 45 degrees toward the associated signal wiring patterns 2. These dummy patterns 1 cross signal wiring patterns 3 formed in another vertically adjacent wiring layer to have an inclination angle of generally 45 degrees. A plurality of dummy patterns 13 are located in the wiring layer in which the signal wiring patterns 3 are formed, so as to be inclined at an angle of generally 45 degrees toward the associated signal wiring patterns 3. The dummy patterns 1 formed in one of the adjacent wiring layers cross the dummy patterns 13 formed in the other wiring layer at an angle of generally 90 degrees. This reduces fluctuations in wiring capacitance and equalizes fluctuations in the wiring capacitance to the maximum extent.

摘要翻译： 当布置虚拟图形以平坦化LSI布局图案时，在其中形成信号布线图案2的布线层中布置多个虚设图案1，以便以相对于相关联的信号布线图案大致45度的角度倾斜 这些虚拟图形1在另一个垂直相邻布线层中形成的交叉信号布线图案3具有大致45度的倾斜角。 多个虚设图形13位于其中形成信号布线图案3的布线层中，以相对于相关联的信号布线图案3以大致45度的角度倾斜。虚设图案1形成为 相邻的布线层以一般为90度的角度与形成在另一布线层中的虚设图案13交叉。 这样可以减少布线电容的波动，并最大限度地均衡布线电容的波动。

公开(公告)号：US5917678A

公开(公告)日：1999-06-29

申请号：US722766

申请日：1996-09-27

申请人： Jun Ito ,  Yoshiyuki Kawakami

发明人： Jun Ito ,  Yoshiyuki Kawakami

IPC分类号： G11B5/41 ,  G11B5/60 ,  G11B11/10 ,  G11B11/105 ,  G11B21/02 ,  G11B21/21

CPC分类号： G11B21/21 ,  G11B5/41 ,  G11B5/6005

摘要： A head slider supporting a read/write head for recording and reproducing information is disposed above a disk, i.e., an information recording medium. The head slider has on its surface facing the disk at least two transversely elongate dynamic pressure generating parts formed with their longer sides extended substantially perpendicularly to the rotating direction of the disk and arranged one behind the other in the rotating direction. The front dynamic pressure generating part is provided with a land of a length in the rotating direction of the disk greater than 10% and smaller than 50%. The land protrudes toward the disk and has a shoulder.

公开(公告)号：US5729469A

公开(公告)日：1998-03-17

申请号：US162353

申请日：1993-12-07

申请人： Yoshiyuki Kawakami

发明人： Yoshiyuki Kawakami

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： The present invention discloses an improved wiring method. Grids are defined at a grid-routing step in such a way that a part of predetermined design criteria are met. Wiring routes are decided on the basis of these grids so that they follow the design criteria and plural functional blocks are connected together. When some nets are left in such a manner that they are assigned no wiring routes, their wiring routes are decided at a non grid-routing step following the design criteria, in defiance of the grids but in accordance with the design criteria. If there are still some nets without wiring routes, their wiring routes are decided at a non grid-routing step ignoring the design criteria. Then, some of the already-defined wiring routes are shoved so as to meet each of the design criteria, and individual wiring patters are generated with respect to all of the decided wiring routes in such a manner that the criteria are met. Even if a greater amount of wiring must be carried out within a smaller area, generation of required wiring patterns can be completed in a short time.

摘要翻译： 本发明公开了一种改进的布线方法。 网格在网格路由步骤中被定义为使得满足预定设计标准的一部分。 接线路由决定于这些网格的基础上，使其符合设计标准，多个功能块连接在一起。 当某些网络以不分配布线路线的方式离开时，其布线路线将按照设计准则在非网格路由步骤中确定，而不依赖于网格，但符合设计标准。 如果仍然有一些没有接线路线的网络，则它们的布线路线将在忽略设计标准的非网格路由步骤中决定。 然后，推出一些已经定义的布线路线，以满足每个设计标准，并且以满足标准的方式，相对于所有决定的布线路线产生单独的布线图案。 即使在更小的区域内必须进行更大量的布线，也可以在短时间内完成所需布线图形的产生。