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公开(公告)号：US07164708B1
公开(公告)日：2007-01-16
申请号：US10031034
申请日：2000-07-12
申请人： Joerg Hauptmann , Christian Schranz , Bernhard Zojer , Peter Pessl , David Schwingshackl , Herbert Zoler
发明人： Joerg Hauptmann , Christian Schranz , Bernhard Zojer , Peter Pessl , David Schwingshackl , Herbert Zoler
IPC分类号： H04B1/38
CPC分类号： H04L27/0002 , H04M11/062
摘要： In the line terminating device, which is provided for transmitting and receiving narrowband low-frequency voice signals and broadband data signals at a higher frequency, the analog reception path is subdivided into two separate analog paths (32, 33) for voice and data using a balance filter (49), which is used for data signal echo cancellation. In the transmission direction, the voice signal path and the data signal path are separated in the digital part by means of digital filters (43, 45). The invention is used for voice and data signal separation in xDSL methods, for example, ADSL.Lite.
摘要翻译： 在用于以更高频率发送和接收窄带低频语音信号和宽带数据信号的线路终端设备中，模拟接收路径被细分为两个单独的模拟路径（32,33），用于语音和数据，使用 平衡滤波器（49），用于数据信号回波消除。 在传输方向上，语音信号路径和数据信号路径通过数字滤波器（43,45）在数字部分中分离。 本发明用于xDSL方法中的语音和数据信号分离，例如ADSL.Lite。
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2.发明授权Device and method for checking whether a signal with a predetermined frequency is being received 失效用于检查是否正在接收到具有预定频率的信号的装置和方法公开(公告)号：US07224751B2
公开(公告)日：2007-05-29
申请号：US10296035
申请日：2001-05-23
IPC分类号： H04L27/14
CPC分类号： H04L27/1563
摘要： A device and method are disclosed, whereby the normally complicated and difficult frequency determination is achieved by simply arranged and executed measures, namely by means of larger, smaller and/or equal comparisons and a counting of certain events. The invention further relates to arrangements whereby the noise signal level, or the influence thereof on the verification to be carried out is reduced.
摘要翻译： 公开了一种装置和方法，由此通过简单的布置和执行的测量，即通过更大，更小和/或等同的比较和某些事件的计数来实现正常复杂和困难的频率确定。 本发明还涉及噪声信号电平或其对要进行的验证的影响减小的布置。
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公开(公告)号：US07002404B2
公开(公告)日：2006-02-21
申请号：US10773710
申请日：2004-02-06
IPC分类号： H03K5/00
CPC分类号： H03H11/1291 , H03H19/008 , H03H2210/021 , H03H2210/043
摘要： The invention relates to a tuning circuit for tuning a filter stage, which has an RC element (1) with an RC time constant (τ), with the RC time constant (τ) being the product of the resistance of a resistor (R1) in the RC element (1) and the capacitance of a capacitor (C1), which is connected in series with the resistor (R1), in the RC element (1), having a comparator (10) for comparison of the voltage which is produced at the potential node (4) between the resistor (R1) and the capacitor (C1), with a reference ground voltage; and having a controller (15) which varies the charge on the capacitor (C1) in the RC element (1) until the comparator (10) indicates that the voltage which is produced at the potential node (4) is equal to the reference ground voltage, with the controller (15) switching a capacitor array (26) as a function of the charge variation time, which capacitor array (26) is connected in parallel with the capacitor (C1) in the RC element (1), in order to compensate for any discrepancy between the RC time constant (τ) of the RC element (1) and a nominal value.
摘要翻译： 本发明涉及一种用于调谐滤波器级的调谐电路，其具有RC时间常数（τ）的RC元件（1），其中RC时间常数（τ）是电阻器（R 1 ）和RC元件（1）中与电阻器（R 1）串联连接的电容器（C1）的电容，具有比较器（10），用于比较 在电阻器（R 1）和电容器（C 1）之间的电位节点（4）产生的具有参考接地电压的电压; 并且具有改变RC元件（1）中的电容器（C1）上的电荷的控制器（15），直到比较器（10）指示在电势节点（4）处产生的电压等于参考 接地电压，控制器（15）根据电荷变化时间切换电容器阵列（26），电容器阵列（26）与RC元件（1）中的电容器（C 1）并联连接， 以便补偿RC元件（1）的RC时间常数（τ）与标称值之间的任何差异。
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公开(公告)号：US06738002B2
公开(公告)日：2004-05-18
申请号：US10229936
申请日：2002-08-28
IPC分类号： H03M120
摘要： A sigma-delta analog-to-digital converter includes an integrator and a dither signal generator for generating a digital dither signal, and a plurality of comparators for converting an analog signal received from the integrator into an output digital value. A digital logic unit is in data communication with the digital dither signal and the comparators. The digital logic unit is configured to change the output digital value on the basis of the digital dither signal.
摘要翻译： Σ-Δ模数转换器包括用于产生数字抖动信号的积分器和抖动信号发生器，以及用于将从积分器接收的模拟信号转换为输出数字值的多个比较器。 数字逻辑单元与数字抖动信号和比较器进行数据通信。 数字逻辑单元被配置为基于数字抖动信号来改变输出数字值。
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公开(公告)号：US06888407B2
公开(公告)日：2005-05-03
申请号：US10233068
申请日：2002-08-31
IPC分类号： H03F3/45
CPC分类号： H03F3/45659 , H03F3/45183 , H03F2203/45514
摘要： The invention relates to a multistage differential amplifier having an input stage, at which a differential input voltage is present, a load connected to the input stage, a CMFB circuit and an output stage, at which an amplified differential output voltage is output. In order to improve the stability of a common-mode regulating loop, a current source is provided, which additionally feeds current into the regulating loop and thereby ensures that a control voltage for the load does not fall below a predetermined value.
摘要翻译： 本发明涉及一种具有输入级的多级差分放大器，存在差分输入电压，连接到输入级的负载，输出级放大的差分输出电压的CMFB电路和输出级。 为了提高共模调节回路的稳定性，提供了电流源，其另外将电流馈送到调节回路中，从而确保负载的控制电压不降至预定值以下。
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公开(公告)号：US07123629B1
公开(公告)日：2006-10-17
申请号：US10031058
申请日：2000-07-13
IPC分类号： H04J3/06
CPC分类号： H04M11/062
摘要： In the broadband network access device for transmitting narrowband, low-frequency voice signals and broadband, higher-frequency data signals, the voice data is sampled in the data clock pattern and subsequently decimated. The transmission of the data which has already been decimated to the voice clock to the voice DSP (DSP) is still carried out in the data clock pattern. The conversion to the voice clock pattern is carried out in a synchronization interface (SM), directly upstream of the voice DSP. The same applies correspondingly in the opposite direction of transmission. The invention is used in xDSL methods, for example ADSL.Lite.
摘要翻译： 在用于传输窄带，低频语音信号和宽带的高频数据信号的宽带网络接入装置中，语音数据以数据时钟模式进行采样，随后抽取。 数据时钟模式仍然执行已经被抽取到语音DSP（DSP）的语音时钟的数据的传输。 在语音DSP的直接上游的同步接口（SM）中进行到语音时钟模式的转换。 相同的方式在相反的传播方向也是一样。 本发明用于xDSL方法，例如ADSL.Lite。
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公开(公告)号：US06340945B1
公开(公告)日：2002-01-22
申请号：US09875971
申请日：2001-06-08
申请人： Jörg Hauptmann , Christian Schranz
发明人： Jörg Hauptmann , Christian Schranz
IPC分类号： H03M112
CPC分类号： H03M3/474
摘要： The present invention is related to an analog/digital converter which includes a multitude of integrating circuits, a 1 bit analog/digital converter and a 1 bit digital/analog converter. The multitude of analog integrating circuits are connected in series and the 1 bit digital/analog converter is connected downstream from the last analog integrating circuit of the series. An output signal of the 1 bit analog/digital converter is transmitted to the 1 bit digital/analog converter, and an output signal of the 1 bit digital/analog converter is subtracted from an input signal of each analog integrating circuit. A multitude of input signals is transmitted via a multiplexer to the first analog integrating circuit of the series-connected analog integrating circuits. Each analog integrating circuit includes a multitude of capacitors which correspond to the multitude of input signals, whereby a capacitor of the multitude of capacitors can be switched each time between an output and an input of the analog integrating circuit. The output signal of the 1 bit digital/analog converter is delayed according to the multitude of input signals.
摘要翻译： 本发明涉及一种包括多个积分电路，1位模拟/数字转换器和1位数字/模拟转换器的模拟/数字转换器。 多个模拟积分电路串联连接，1位数/模转换器连接在该系列的最后一个模拟积分电路的下游。 1位模拟/数字转换器的输出信号被传送到1位数/模转换器，并从每个模拟积分电路的输入信号中减去1位数/模转换器的输出信号。 多个输入信号通过多路复用器传输到串联模拟积分电路的第一模拟积分电路。 每个模拟积分电路包括对应于多个输入信号的多个电容器，由此可以每次在模拟积分电路的输出和输入之间切换多个电容器的电容器。 1位数/模转换器的输出信号根据输入信号的大小而被延迟。
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