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    Reduced impact from coupling noise in diagonal bitline architectures
    3.
    发明授权
    Reduced impact from coupling noise in diagonal bitline architectures 有权
    减少对角位线结构中耦合噪声的影响

    公开(公告)号：US06320780B1

    公开(公告)日：2001-11-20

    申请号：US09406892

    申请日：1999-09-28

    申请人： Gerhard Mueller ,  Ulrike Gruening

    发明人： Gerhard Mueller ,  Ulrike Gruening

    IPC分类号： G11C506

    CPC分类号： H01L27/10805 ,  G11C11/4097 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit comprising first and second adjacent signal line pairs 310 and 320 is described. The signal line pairs comprise diagonal signal paths 311p, 312p; 321p and 322p with directional changes 335. The first signal line pair comprises m twists 340, where m is a whole number ≧1, and the second signal line pair comprises n twists 360 and 361, where n is a whole number ≠m.

    摘要翻译： 描述了包括第一和第二相邻信号线对310和320的集成电路。 信号线对包括对角线信号路径311p，312p; 321p和322p具有方向改变335.第一信号线对包括m个扭曲340，其中m是整数> = 1，第二信号线对包括n个捻度360和361，其中n是整数m 。

    Reducing impact of coupling noise in multi-level bitline architecture
    4.
    发明授权
    Reducing impact of coupling noise in multi-level bitline architecture 有权
    减少耦合噪声对多级位线架构的影响

    公开(公告)号：US06327170B1

    公开(公告)日：2001-12-04

    申请号：US09406890

    申请日：1999-09-28

    申请人： Gerhard Mueller ,  Ulrike Gruening

    发明人： Gerhard Mueller ,  Ulrike Gruening

    IPC分类号： G11C508

    CPC分类号： G11C11/4097

    摘要： An integrated circuit comprising first and second bitline pairs 410 and 420 is described. The bitline paths of a bitline pair are on different bitline levels. The bitline paths of the first and second bitline pairs which are on different bitline levels are adjacent to each other. The first bitline pair comprises m vertical-horizontal twists 440, where m is a whole number≧1, and the second bitline pair comprises n vertical-horizontal twists 460 and 461, where n is a whole number≠m. The vertical-horizontal twists transform coupling noise into common mode noise.

    摘要翻译： 描述了包括第一和第二位线对410和420的集成电路。 位线对的位线路径位于不同的位线上。 处于不同位线电平的第一和第二位线对的位线路径彼此相邻。 第一位线对包括m垂直水平扭转440，其中m是整数> = 1，第二位线对包括n个垂直 - 水平扭转460和461，其中n是整数m。 垂直水平扭转将耦合噪声转换为共模噪声。

    Locally folded split level bitline wiring
    5.
    发明授权
    Locally folded split level bitline wiring 有权
    本地折叠裂缝级位线接线

    公开(公告)号：US06291335B1

    公开(公告)日：2001-09-18

    申请号：US09411551

    申请日：1999-10-04

    申请人： Rainer Florian Schnabel ,  Ulrike Gruening ,  Thomas Rupp ,  Gerhard Mueller

    发明人： Rainer Florian Schnabel ,  Ulrike Gruening ,  Thomas Rupp ,  Gerhard Mueller

    IPC分类号： H01L214763

    CPC分类号： H01L27/10885 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/28525 ,  H01L21/76807 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/10888 ,  H01L27/10894

    摘要： A method for fabricating a semiconductor memory with a split level folded bitline structure consisting of three contact levels, in accordance with the present invention includes forming gate structures for transistors in an array region and a support region of a substrate. First contacts are formed down to diffusion regions between the gate structures in the array region. The first contacts have a height which is substantially the same for all first contacts in the array region. Second contacts are formed between first level bitlines in the array region and a first portion of the first contacts, while forming second contacts to a first metal layer from the gate structures and diffusion regions in the support region. Third contacts are formed between second level bitlines in the array region and a second portion of the first contacts, while forming third contacts to a second metal layer from the first metal layer in the support region.

    摘要翻译： 根据本发明的用于制造具有由三个接触电平组成的分裂电平折叠位线结构的半导体存储器的方法包括在阵列区域和衬底的支撑区域中形成用于晶体管的栅极结构。 第一触点形成在阵列区域中的栅极结构之间的扩散区域。 第一触点具有与阵列区域中的所有第一触点基本相同的高度。 在阵列区域的第一级位线和第一触点的第一部分之间形成第二触点，同时从支撑区域中的栅极结构和扩散区域形成第二触点到第一金属层。 在支撑区域中从第一金属层形成与第二金属层形成第三触点的第三触点形成在阵列区域中的第二电平位线和第一触点的第二部分之间。

    Reducing impact of coupling noise
    6.
    发明授权
    Reducing impact of coupling noise 失效
    降低耦合噪声的影响

    公开(公告)号：US06188598B1

    公开(公告)日：2001-02-13

    申请号：US09406891

    申请日：1999-09-28

    申请人： Gerhard Mueller ,  Ulrike Gruening

    发明人： Gerhard Mueller ,  Ulrike Gruening

    IPC分类号： G11C506

    CPC分类号： G11C7/18

    摘要： An integrated circuit comprising a first bitline pair 310 on a first bitline level which is adjacent to a second bitline pair 320 on a second bitline level is provided. The first bitline pair comprises m twists 340, where m is a whole number≧1 and the second bitline pair comprises n twists 350 and 351, where n is a whole number ≠m. The twists transform coupling noise from adjacent bitline pairs into common mode noise, which results in improved signal margin.

    摘要翻译： 提供了一种集成电路，其包括与第二位线电平上的第二位线对320相邻的第一位线电平上的第一位线对310。 第一位线对包括m个扭曲340，其中m是整数> = 1，第二位线对包括n个扭曲350和351，其中n是整数m。 扭曲将来自相邻位线对的耦合噪声转换为共模噪声，这导致改善的信号余量。

    Conductive lines with reduced pitch
    8.
    发明授权
    Conductive lines with reduced pitch 有权
    具有减小节距的导电线

    公开(公告)号：US06469392B2

    公开(公告)日：2002-10-22

    申请号：US09751492

    申请日：2000-12-28

    申请人： Young-Jin Park ,  Gerhard Mueller

    发明人： Young-Jin Park ,  Gerhard Mueller

    IPC分类号： H01L23528

    CPC分类号： H01L23/5222 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit having conductive lines with non-rectangular shaped cross-sections. The non-rectangular shaped cross-sections facilitate a reduction in line pitch without increasing capacitive coupling noise between adjacent conductive lines or, alternatively, reduction in capacitive coupling noise between adjacent lines for a given pitch.

    摘要翻译： 一种具有非矩形横截面的导线的集成电路。 非矩形横截面有助于减小线间距，而不会增加相邻导线之间的电容耦合噪声，或者替代地，减小给定间距的相邻线之间的电容耦合噪声。

    Optical module for simultaneously focusing on two fields of view
    9.
    发明授权
    Optical module for simultaneously focusing on two fields of view 有权
    用于同时聚焦于两个视野的光学模块

    公开(公告)号：US09040915B2

    公开(公告)日：2015-05-26

    申请号：US13382405

    申请日：2010-06-22

    申请人： Konrad Rothenhaeusler ,  Gerhard Mueller ,  Lutz Kuehnke

    发明人： Konrad Rothenhaeusler ,  Gerhard Mueller ,  Lutz Kuehnke

    IPC分类号： G01J1/44 ,  G01J5/20 ,  G01J1/06 ,  H04N5/225 ,  B60S1/08

    CPC分类号： H04N5/2254 ,  B60S1/0844 ,  G06K9/00791

    摘要： The invention relates to an optical module, comprising a semiconductor element having a surface that is sensitive to electromagnetic radiation and an objective for projecting electromagnetic radiation onto the sensitive surface of the semiconductor element (image sensor or camera chip, in particular CCD or CMOS). The objective preferably comprises at least one lens and one lens retainer.In the optical module, an optical element having two sub-areas is arranged either in the space between the objective and the sensitive surface of the semiconductor element or between individual lenses of the objective in the entire cross-section of the beam path. All electromagnetic radiation that reaches the sensitive surface of the semiconductor element passes through the optical element.A first distance range (e.g. near range) is imaged in a first area of the sensitive surface of the semiconductor element in a focused manner by a first sub-area of the optical element, and a second distance range (e.g. far range) is imaged in a second area of the sensitive surface of the semiconductor element by a second sub-area.

    摘要翻译： 本发明涉及一种光学模块，包括具有对电磁辐射敏感的表面的半导体元件和用于将电磁辐射投射到半导体元件（图像传感器或照相机芯片，特别是CCD或CMOS）的敏感表面上的物镜。 该目的优选地包括至少一个透镜和一个透镜保持器。 在光学模块中，具有两个子区域的光学元件被布置在物镜和半导体元件的敏感表面之间的空间中，或者布置在光束路径的整个横截面中的物镜的各个透镜之间。 到达半导体元件的敏感表面的所有电磁辐射通过光学元件。 将第一距离范围（例如近距离）以聚焦方式由该光学元件的第一子区域成像在半导体元件的敏感表面的第一区域中，并且第二距离范围（例如，远距离）被成像 在第二子区域的半导体元件的敏感表面的第二区域中。