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公开(公告)号：US20120218814A1
公开(公告)日：2012-08-30
申请号：US13034936
申请日：2011-02-25
CPC分类号： G11C7/1012 , G06F2213/0038 , G11C13/0004 , G11C13/0069 , G11C2013/008
摘要： A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.
摘要翻译： 一种存储器系统，其包括具有由可变写入时间表征的存储器单元的多个存储器阵列。 存储器系统还包括被配置为接收写入命令的存储器总线以及被配置为与存储器阵列进行通信的多个数据缓冲器。 存储器系统还包括配置为与存储器阵列通信以存储写入地址的地址缓冲器。 被配置为接收写入命令并将用写入命令接收的数据线分割成多个部件的机构也包括在存储器系统中。 数据线的部分存储在不同的数据缓冲器中，并且开始将写入地址的数据线的部分写入存储器阵列。 当从所有存储器阵列接收到指定写入地址的写入完成信号时，写入命令完成。
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公开(公告)号：US08374040B2
公开(公告)日：2013-02-12
申请号：US13034936
申请日：2011-02-25
IPC分类号： G11C7/00
CPC分类号： G11C7/1012 , G06F2213/0038 , G11C13/0004 , G11C13/0069 , G11C2013/008
摘要： A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.
摘要翻译： 一种存储器系统，其包括具有由可变写入时间表征的存储器单元的多个存储器阵列。 存储器系统还包括被配置为接收写入命令的存储器总线以及被配置为与存储器阵列进行通信的多个数据缓冲器。 存储器系统还包括配置为与存储器阵列通信以存储写入地址的地址缓冲器。 被配置为接收写入命令并将用写入命令接收的数据线分割成多个部件的机构也包括在存储器系统中。 数据线的部分存储在不同的数据缓冲器中，并且开始将写入地址的数据线的部分写入存储器阵列。 当从所有存储器阵列接收到指定写入地址的写入完成信号时，写入命令完成。
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公开(公告)号：US08897062B2
公开(公告)日：2014-11-25
申请号：US13150690
申请日：2011-06-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译： 提供了用于向内存位置迭代地写入内容的系统，方法和设备。 统计模型用于确定将所需内容写入存储器位置的脉冲序列。 内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。 对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。 读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。 统计模型和查询表可用于选择和修改脉冲。 自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。
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4.发明授权Constrained coding to reduce floating gate coupling in non-volatile memories 失效约束编码以减少非易失性存储器中的浮动栅极耦合公开(公告)号：US08463985B2
公开(公告)日：2013-06-11
申请号：US12751197
申请日：2010-03-31
CPC分类号： G11C16/0483 , G06F12/0246 , G06F2212/7202 , G11C7/1006 , G11C16/10
摘要： Constrained coding to reduce floating gate coupling in non-volatile memories including a method for storing data. The method includes receiving write data to be written to a flash memory device, selecting a codeword in response to the write data, and writing the codeword to the flash memory device. The codeword is selected to reduce floating gate coupling in the flash memory device by preventing specified symbol patterns from occurring in the codeword.
摘要翻译： 约束编码以减少非易失性存储器中的浮动栅极耦合，包括用于存储数据的方法。 该方法包括接收要写入闪速存储器件的写入数据，响应写入数据选择一个代码字，以及将该代码字写入闪存器件。 选择码字以通过防止在码字中发生指定的符号模式来减少闪存器件中的浮动栅极耦合。
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5.发明申请ADAPTIVE WEAR LEVELING VIA MONITORING THE PROPERTIES OF MEMORY REFERENCE STREAM 有权通过监测记忆参考流的性质，自适应磨损公开(公告)号：US20130013886A1
公开(公告)日：2013-01-10
申请号：US13619513
申请日：2012-09-14
IPC分类号： G06F12/10
CPC分类号： G06F12/0246 , G06F2212/1052 , G06F2212/7201 , G06F2212/7211
摘要： Adaptive write leveling in limited lifetime memory devices including performing a method for monitoring a write data stream that includes write line addresses. A property of the write data stream is detected and a write leveling process is adapted in response to the detected property. The write leveling process is applied to the write data stream to generate physical addresses from the write line addresses.
摘要翻译： 在有限寿命的存储器设备中的自适应写平均化，包括执行用于监视包括写入行地址的写入数据流的方法。 检测写入数据流的属性，并响应于检测到的属性来调整写入调平过程。 写入平均过程被应用于写入数据流以从写入地址生成物理地址。
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公开(公告)号：US20130013860A1
公开(公告)日：2013-01-10
申请号：US13619451
申请日：2012-09-14
申请人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
CPC分类号： G06F12/00 , G06F12/08 , G06F12/0802 , G06F12/0891
摘要： Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.
摘要翻译： 用于改进性能的存储单元预设，包括使用计算机系统识别存储器中的区域的方法。 该区域包括多个存储单元，其特征在于当写入操作将存储单元的当前状态改变到存储单元的期望状态时具有第一期望值的写入性能特性，以及当写入操作改变时第二预期值 存储器单元的指定状态到存储器单元的期望状态。 第二期望值比第一期望值更接近写入性能特性的期望值。 区域中的多个存储单元被设置为指定状态，并且响应于该设置将数据写入多个存储单元。
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公开(公告)号：US08352839B2
公开(公告)日：2013-01-08
申请号：US12814142
申请日：2010-06-11
IPC分类号： H03M13/00
CPC分类号： G11C13/0004 , G11C7/1006 , G11C13/00 , G11C13/0069
摘要： Encoding data into constrained memory using a method for writing data that includes receiving write data to be encoded into a write word, receiving constraints on symbol values associated with the write word, encoding the write data into the write word, and writing the write word to a memory. The encoding includes: representing the write data and the constraints as a first linear system in a first field of a first size; embedding the first linear system into a second linear system in a second field of a second size, the second size larger than the first size; solving the second linear system in the second field resulting in a solution; and collapsing the solution into the first field resulting in the write word, the write word satisfying the constraints on symbol values associated with the write word.
摘要翻译： 使用用于写入数据的方法将数据编码到约束存储器中，该方法包括接收要编码的写入数据到写入字中，接收与写入字相关联的符号值的约束，将写入数据编码到写入字中，以及将写入字写入 一个记忆 编码包括：在第一尺寸的第一场中表示作为第一线性系统的写入数据和约束; 在第二尺寸的第二场中将第一线性系统嵌入第二线性系统中，第二尺寸大于第一尺寸; 求解第二个场中的第二个线性系统，得到解决方案; 并且将解决方案折叠到第一场中，导致写入字，写入字满足与写入字相关联的符号值的约束。
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公开(公告)号：US20120290898A1
公开(公告)日：2012-11-15
申请号：US13556275
申请日：2012-07-24
CPC分类号： G06F12/0246 , G06F11/1012 , G06F2212/1036 , G06F2212/401 , G06F2212/403 , G06F2212/7207 , G11C16/349
摘要： Adaptive endurance coding including a method for accessing memory that includes retrieving a codeword from a memory address. The codeword is multiplied by a metadata matrix to recover metadata for the codeword. The metadata includes a data location specification. The data in the codeword is identified in response to the metadata and the data is output as read data.
摘要翻译： 适应性耐力编码包括用于访问存储器的方法，包括从存储器地址检索码字。 将码字乘以元数据矩阵以恢复码字的元数据。 元数据包括数据位置规范。 代码字中的数据是响应于元数据而被识别的，数据被输出为读取数据。
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公开(公告)号：US20120287714A1
公开(公告)日：2012-11-15
申请号：US13557298
申请日：2012-07-25
申请人： Ibrahim M. Elfadel , Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
CPC分类号： G11C29/08 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2211/5641
摘要： Providing increased capacity in heterogeneous storage elements including a method for reading from memory. The method includes receiving a read word from a block of memory cells, where physical characteristics of the memory cells support different sets of data levels. The read word is separated into two or more virtual read vectors. For each of the virtual read vectors, the codebook that was utilized to generate the virtual read vector is identified and a partial read data vector is generated. The generating includes multiplying the virtual read vector by a matrix that represents the codebook. The partial read data vectors are combined into a read message and the read message is output.
摘要翻译： 在异构存储元件中提供增加的容量，包括从存储器读取的方法。 该方法包括从存储器单元块接收读取字，其中存储器单元的物理特性支持不同数据级的集合。 读取的字被分成两个或更多个虚拟读取向量。 对于每个虚拟读取向量，识别用于生成虚拟读取向量的码本，并生成部分读取数据向量。 生成包括将虚拟读取向量乘以代表码本的矩阵。 将部分读取数据矢量组合成读取消息，并输出读出的消息。
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10.发明授权公开(公告)号：US08176235B2
公开(公告)日：2012-05-08
申请号：US12631505
申请日：2009-12-04
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： Enhanced write performance for non-volatile memories including a memory system that includes a receiver for receiving a data rate of a data sequence to be written to a non-volatile flash memory device. The memory system also includes a physical page selector for selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, and for determining if the number of free bits in the invalid previously written memory page at the selected physical address is greater than or equal to the data rate. The memory system also includes a transmitter for outputting the selected physical address of the invalid previously written memory page, the outputting in response to the physical page selector determining that the number of free bits is greater than or equal to the data rate.
摘要翻译： 对于非易失性存储器的增强的写入性能，包括存储器系统，该存储器系统包括用于接收要写入非易失性闪速存储器件的数据序列的数据速率的接收器。 存储器系统还包括物理页面选择器，用于从位于非易失性存储器设备上的无效的先前写入的存储器页面的一组物理地址中选择无效的先前写入的存储器页面的物理地址，并且用于确定是否有空闲数量 在所选物理地址处的无效的先前写入的存储器页中的位大于或等于数据速率。 存储器系统还包括用于输出无效的先前写入的存储器页面的所选物理地址的发射器，响应于物理页选择器确定空闲位的数量大于或等于数据速率的输出。
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