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    SOLID-STATE DEVICE MANAGEMENT
    2.
    发明申请
    SOLID-STATE DEVICE MANAGEMENT 审中-公开
    固态设备管理

    公开(公告)号：US20130166826A1

    公开(公告)日：2013-06-27

    申请号：US13619424

    申请日：2012-09-14

    申请人： Michele M. Franceschini ,  Ashish Jagmohan

    发明人： Michele M. Franceschini ,  Ashish Jagmohan

    IPC分类号： G06F12/00

    CPC分类号： G06F3/0688 ,  G06F3/0601 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0652 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7211

    摘要： An embodiment is a method for establishing a correspondence between a first logical address and a first physical address on solid-state storage devices located on a solid-state storage board. The solid-state storage devices include a plurality of physical memory locations identified by physical addresses, and the establishing is by a software module located on a main board that is separate from the solid-state storage board. The correspondence between the first logical address and the first physical address is stored in in a location on a solid-state memory device that is accessible by an address translator module located on the solid-state storage board. The solid-state memory device is located on the solid-state storage board. The first logical address is translated to the first physical address by the address translator module based on the previously established correspondence between the first logical address and the first physical address.

    摘要翻译： 一个实施例是用于在固态存储板上的固态存储设备上建立第一逻辑地址和第一物理地址之间的对应关系的方法。 固态存储装置包括通过物理地址识别的多个物理存储器位置，并且由位于与固态存储板分离的主板上的软件模块建立。 第一逻辑地址和第一物理地址之间的对应关系存储在固态存储设备上的位于固态存储板上的地址转换器模块可访问的位置。 固态存储器件位于固态存储板上。 基于先前建立的第一逻辑地址和第一物理地址之间的对应关系，地址转换器模块将第一逻辑地址转换为第一物理地址。

    Write bandwidth in a memory characterized by a variable write time
    4.
    发明授权
    Write bandwidth in a memory characterized by a variable write time 有权
    将带宽写入以可变写入时间为特征的存储器中

    公开(公告)号：US08374040B2

    公开(公告)日：2013-02-12

    申请号：US13034936

    申请日：2011-02-25

    申请人： John A. Bivens ,  Michele M. Franceschini ,  Luis A. Lastras-Montano

    发明人： John A. Bivens ,  Michele M. Franceschini ,  Luis A. Lastras-Montano

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1012 ,  G06F2213/0038 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/008

    摘要： A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.

    摘要翻译： 一种存储器系统，其包括具有由可变写入时间表征的存储器单元的多个存储器阵列。 存储器系统还包括被配置为接收写入命令的存储器总线以及被配置为与存储器阵列进行通信的多个数据缓冲器。 存储器系统还包括配置为与存储器阵列通信以存储写入地址的地址缓冲器。 被配置为接收写入命令并将用写入命令接收的数据线分割成多个部件的机构也包括在存储器系统中。 数据线的部分存储在不同的数据缓冲器中，并且开始将写入地址的数据线的部分写入存储器阵列。 当从所有存储器阵列接收到指定写入地址的写入完成信号时，写入命令完成。

    PLANAR PHASE- CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS
    5.
    发明申请
    PLANAR PHASE- CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS 有权
    平面相变记忆电池与并联电气

    公开(公告)号：US20130016556A1

    公开(公告)日：2013-01-17

    申请号：US13619473

    申请日：2012-09-14

    申请人： Michele M. Franceschini ,  John P. Karidis

    发明人： Michele M. Franceschini ,  John P. Karidis

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0083 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/1675

    摘要： A method for operating a phase change memory that includes initializing a memory cell that includes: a first conductive electrode having a length greater than its width and an axis aligned with the length; a second conductive electrode having an edge oriented at an angle to the axis of the first conductive electrode; an insulator providing a separation distance between an end of the first conductive electrode and the edge of the second conductive electrode; and a phase change material covering a substantial portion of the first conductive electrode and at least a portion of the second conductive electrode. The initializing the memory cell includes creating a first amorphous material region in the phase change material. An active crystalline material region is created inside the first amorphous material region. Information is stored in the memory cell by creating a second amorphous material region inside the active crystalline material region.

    摘要翻译： 一种用于操作相变存储器的方法，包括初始化存储单元，所述存储单元包括：具有大于其宽度的长度的第一导电电极和与所述长度对准的轴线; 第二导电电极，其具有与第一导电电极的轴成一定角度的边缘; 绝缘体，其在所述第一导电电极的端部和所述第二导电电极的边缘之间提供间隔距离; 以及覆盖所述第一导电电极的主要部分和所述第二导电电极的至少一部分的相变材料。 初始化存储单元包括在相变材料中形成第一非晶态材料区域。 在第一无定形材料区域内形成活性结晶材料区域。 通过在活性结晶材料区域内产生第二非晶态材料区域将信息存储在存储器单元中。

    MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE
    7.
    发明申请
    MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE 有权
    用于改善记忆性能的存储单元预置

    公开(公告)号：US20130013860A1

    公开(公告)日：2013-01-10

    申请号：US13619451

    申请日：2012-09-14

    申请人： Michele M. Franceschini ,  Ashish Jagmohan ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi

    发明人： Michele M. Franceschini ,  Ashish Jagmohan ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi

    IPC分类号： G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0891

    摘要： Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.

    摘要翻译： 用于改进性能的存储单元预设，包括使用计算机系统识别存储器中的区域的方法。 该区域包括多个存储单元，其特征在于当写入操作将存储单元的当前状态改变到存储单元的期望状态时具有第一期望值的写入性能特性，以及当写入操作改变时第二预期值 存储器单元的指定状态到存储器单元的期望状态。 第二期望值比第一期望值更接近写入性能特性的期望值。 区域中的多个存储单元被设置为指定状态，并且响应于该设置将数据写入多个存储单元。

    Encoding data into constrained memory
    8.
    发明授权
    Encoding data into constrained memory 失效
    将数据编码到受限内存中

    公开(公告)号：US08352839B2

    公开(公告)日：2013-01-08

    申请号：US12814142

    申请日：2010-06-11

    申请人： Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Mayank Sharma

    发明人： Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Mayank Sharma

    IPC分类号： H03M13/00

    CPC分类号： G11C13/0004 ,  G11C7/1006 ,  G11C13/00 ,  G11C13/0069

    摘要： Encoding data into constrained memory using a method for writing data that includes receiving write data to be encoded into a write word, receiving constraints on symbol values associated with the write word, encoding the write data into the write word, and writing the write word to a memory. The encoding includes: representing the write data and the constraints as a first linear system in a first field of a first size; embedding the first linear system into a second linear system in a second field of a second size, the second size larger than the first size; solving the second linear system in the second field resulting in a solution; and collapsing the solution into the first field resulting in the write word, the write word satisfying the constraints on symbol values associated with the write word.

    摘要翻译： 使用用于写入数据的方法将数据编码到约束存储器中，该方法包括接收要编码的写入数据到写入字中，接收与写入字相关联的符号值的约束，将写入数据编码到写入字中，以及将写入字写入 一个记忆 编码包括：在第一尺寸的第一场中表示作为第一线性系统的写入数据和约束; 在第二尺寸的第二场中将第一线性系统嵌入第二线性系统中，第二尺寸大于第一尺寸; 求解第二个场中的第二个线性系统，得到解决方案; 并且将解决方案折叠到第一场中，导致写入字，写入字满足与写入字相关联的符号值的约束。

    INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS
    10.
    发明申请
    INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS 有权
    增加容量异质存储元素

    公开(公告)号：US20120287714A1

    公开(公告)日：2012-11-15

    申请号：US13557298

    申请日：2012-07-25

    申请人： Ibrahim M. Elfadel ,  Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Mayank Sharma

    发明人： Ibrahim M. Elfadel ,  Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Mayank Sharma

    IPC分类号： G11C7/00 ,  G11C11/00 ,  G11C16/04

    CPC分类号： G11C29/08 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2211/5641

    摘要： Providing increased capacity in heterogeneous storage elements including a method for reading from memory. The method includes receiving a read word from a block of memory cells, where physical characteristics of the memory cells support different sets of data levels. The read word is separated into two or more virtual read vectors. For each of the virtual read vectors, the codebook that was utilized to generate the virtual read vector is identified and a partial read data vector is generated. The generating includes multiplying the virtual read vector by a matrix that represents the codebook. The partial read data vectors are combined into a read message and the read message is output.

    摘要翻译： 在异构存储元件中提供增加的容量，包括从存储器读取的方法。 该方法包括从存储器单元块接收读取字，其中存储器单元的物理特性支持不同数据级的集合。 读取的字被分成两个或更多个虚拟读取向量。 对于每个虚拟读取向量，识别用于生成虚拟读取向量的码本，并生成部分读取数据向量。 生成包括将虚拟读取向量乘以代表码本的矩阵。 将部分读取数据矢量组合成读取消息，并输出读出的消息。