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    Method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between components
    1.
    发明授权
    Method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between components 失效
    用于生成用于识别耦合在组件之间的硬件设备中的关键定时路径的定时路径软件监视器的方法

    公开(公告)号：US07467366B2

    公开(公告)日：2008-12-16

    申请号：US11535203

    申请日：2006-09-26

    申请人： John B. Blankenship ,  Kevin N. Magill ,  Jeffrey R. Summers ,  Anup Wadia

    发明人： John B. Blankenship ,  Kevin N. Magill ,  Jeffrey R. Summers ,  Anup Wadia

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between first and second components is provided. The method includes generating a static timing report associated with the hardware devices. The static timing report has names of the hardware devices and wire names associated with wires coupled to the hardware devices. The method further includes automatically generating the timing path software monitor based on the static timing report that monitors binary values associated with the wire names at a first clock cycle and a transition of binary values associated with the wire names during a second clock cycle after the first clock cycle. The timing path software monitor indicates a critical timing path is identified when the transition of one of the binary values received by the second component occurs during the second clock cycle.

    摘要翻译： 提供了一种用于生成用于识别耦合在第一和第二组件之间的硬件设备中的关键定时路径的定时路径软件监视器的方法。 该方法包括生成与硬件设备相关联的静态定时报告。 静态定时报告具有与耦合到硬件设备的线路相关联的硬件设备和线名称。 该方法还包括基于静态定时报告自动生成定时路径软件监视器，静态定时报告在第一时钟周期监视与线名称相关联的二进制值，以及在第一时钟周期之后的第二时钟周期期间与线名相关联的二进制值的转变 时钟周期。 定时路径软件监视器指示当在第二时钟周期期间发生由第二分量接收的二进制值之一的转换时，识别关键定时路径。

    METHOD FOR GENERATING A TIMING PATH SOFTWARE MONITOR FOR IDENTIFYING A CRITICAL TIMING PATH IN HARDWARE DEVICES COUPLED BETWEEN COMPONENTS
    2.
    发明申请
    METHOD FOR GENERATING A TIMING PATH SOFTWARE MONITOR FOR IDENTIFYING A CRITICAL TIMING PATH IN HARDWARE DEVICES COUPLED BETWEEN COMPONENTS 失效
    用于识别在组件之间耦合的硬件设备中的关键时序路径的定时路径软件监视器的方法

    公开(公告)号：US20080077895A1

    公开(公告)日：2008-03-27

    申请号：US11535203

    申请日：2006-09-26

    申请人： John B. Blankenship ,  Kevin N. Magill ,  Jeffrey R. Summers ,  Anup Wadia

    发明人： John B. Blankenship ,  Kevin N. Magill ,  Jeffrey R. Summers ,  Anup Wadia

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5031

    摘要： A method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between first and second components is provided. The method includes generating a static timing report associated with the hardware devices. The static timing report has names of the hardware devices and wire names associated with wires coupled to the hardware devices. The method further includes automatically generating the timing path software monitor based on the static timing report that monitors binary values associated with the wire names at a first clock cycle and a transition of binary values associated with the wire names during a second clock cycle after the first clock cycle. The timing path software monitor indicates a critical timing path is identified when the transition of one of the binary values received by the second component occurs during the second clock cycle.

    摘要翻译： 提供了一种用于生成用于识别耦合在第一和第二组件之间的硬件设备中的关键定时路径的定时路径软件监视器的方法。 该方法包括生成与硬件设备相关联的静态定时报告。 静态定时报告具有与耦合到硬件设备的线路相关联的硬件设备和线名称。 该方法还包括基于静态定时报告自动生成定时路径软件监视器，静态定时报告在第一时钟周期监视与线名称相关联的二进制值，以及在第一时钟周期之后的第二时钟周期期间与线名相关联的二进制值的转变 时钟周期。 定时路径软件监视器指示当在第二时钟周期期间发生由第二分量接收的二进制值之一的转换时，识别关键定时路径。

    Method and apparatus for dynamically managing instruction buffer depths for non-predicted branches
    4.
    发明授权
    Method and apparatus for dynamically managing instruction buffer depths for non-predicted branches 失效
    用于动态管理非预测分支的指令缓冲区深度的方法和装置

    公开(公告)号：US07779232B2

    公开(公告)日：2010-08-17

    申请号：US11845838

    申请日：2007-08-28

    申请人： Richard W. Doing ,  Michael O. Klett ,  Kevin N. Magill ,  Brian R. Mestan ,  David Mui ,  Balaram Sinharoy ,  Jeffrey R. Summers

    发明人： Richard W. Doing ,  Michael O. Klett ,  Kevin N. Magill ,  Brian R. Mestan ,  David Mui ,  Balaram Sinharoy ,  Jeffrey R. Summers

    IPC分类号： G06F9/42 ,  G06F9/312

    CPC分类号： G06F9/3804

    摘要： A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.

    摘要翻译： 用于动态管理非预测分支的指令缓冲器深度的方法和装置减少与低置信度分支预测条件相关联的浪费的能量和资源。 分配用于指令线程的指令缓冲器的一部分用于存储预测的分支指令流，并且在高预测置信度条件下可以为零大小的另一部分被分配给非预测分支指令流。 缓冲区的大小根据正在进行的预测置信度动态调整，提供了分支预测机制对给定指令线程的工作原理的测量。 替代指令提取地址表可以与主提取地址寄存器保持多路复用，用于对指令高速缓存进行寻址，使得当分支指令被解析为非预测路径时，可以将指令流快速移位到非预测路径 。

    Method and Apparatus for Dynamically Managing Instruction Buffer Depths for Non-Predicted Branches
    6.
    发明申请
    Method and Apparatus for Dynamically Managing Instruction Buffer Depths for Non-Predicted Branches 失效
    用于动态管理非预测分支的指令缓冲区深度的方法和装置

    公开(公告)号：US20090063819A1

    公开(公告)日：2009-03-05

    申请号：US11845838

    申请日：2007-08-28

    申请人： Richard W. Doing ,  Michael O. Klett ,  Kevin N. Magill ,  Brian R. Mestan ,  David Mui ,  Balaram Sinharoy ,  Jeffrey R. Summers

    发明人： Richard W. Doing ,  Michael O. Klett ,  Kevin N. Magill ,  Brian R. Mestan ,  David Mui ,  Balaram Sinharoy ,  Jeffrey R. Summers

    IPC分类号： G06F9/312 ,  G06F9/38

    CPC分类号： G06F9/3804

    摘要： A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.

    摘要翻译： 用于动态管理非预测分支的指令缓冲器深度的方法和装置减少与低置信度分支预测条件相关联的浪费的能量和资源。 分配用于指令线程的指令缓冲器的一部分用于存储预测的分支指令流，并且在高预测置信度条件下可以为零大小的另一部分被分配给非预测分支指令流。 缓冲区的大小根据正在进行的预测置信度动态调整，提供了分支预测机制对给定指令线程的工作原理的测量。 替代指令提取地址表可以与主提取地址寄存器保持多路复用，用于对指令高速缓存进行寻址，使得当分支指令被解析为非预测路径时，可以将指令流快速移位到非预测路径 。

    Power-efficient thread priority enablement
    8.
    发明授权
    Power-efficient thread priority enablement 有权
    高效的线程优先级启用

    公开(公告)号：US08261276B2

    公开(公告)日：2012-09-04

    申请号：US12059576

    申请日：2008-03-31

    申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Richard James Eickemeyer ,  Susan Elizabeth Eisen ,  Michael Stephen Floyd ,  Hans Mikael Jacobson ,  Jeffrey R. Summers

    发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Richard James Eickemeyer ,  Susan Elizabeth Eisen ,  Michael Stephen Floyd ,  Hans Mikael Jacobson ,  Jeffrey R. Summers

    IPC分类号： G06F9/46 ,  G06F9/00 ,  G06F13/28 ,  G06F1/32

    CPC分类号： G06F9/4893 ,  Y02D10/24

    摘要： A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.

    摘要翻译： 一种用于控制在线程切换控制寄存器中的指令获取和调度线程优先级设置的机制，用于减少平衡刷新的发生和调度刷新以提高同时多线程数据处理系统的功率性能。 为了实现处理器的目标功率效率模式，说明性实施例从较高级系统控制器接收指令或命令以设置处理器的当前功耗。 说明性实施例确定了处理器的目标功率效率模式。 一旦确定了目标功率模式，则说明性实施例更新用于执行线程的线程切换控制寄存器中的线程优先级设置，以控制平衡冲突推测和调度冲销推测以实现目标功率效率模式。