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1.发明授权公开(公告)号：US07737983B2
公开(公告)日：2010-06-15
申请号：US11552693
申请日：2006-10-25
CPC分类号： G06F9/542 , G06F9/3879 , G06F9/485 , G06F9/526 , G06T1/20
摘要： A method for high level synchronization between an application and a graphics pipeline comprises receiving an application instruction in an input stream at a predetermined component, such as a command stream processor (CSP), as sent by a central processing unit. The CSP may have a first portion coupled to a next component in the graphics pipeline and a second portion coupled to a plurality of components of the graphics pipeline. A command associated with the application instruction may be forwarded from the first portion to the next component in the graphics pipeline or some other component coupled thereto. The command may be received and thereafter executed. A response may be communicated on a feedback path to the second portion of the CSP. Nonlimiting exemplary application instructions that may be received and executed by the CSP include check surface fault, trap, wait, signal, stall, flip, and trigger.
摘要翻译： 一种用于应用程序和图形流水线之间的高级别同步的方法包括：在由中央处理单元发送的诸如命令流处理器（CSP）的预定组件的输入流中接收应用程序指令。 CSP可以具有耦合到图形流水线中的下一个组件的第一部分和耦合到图形流水线的多个组件的第二部分。 与应用指令相关联的命令可以从第一部分转发到图形流水线中的下一个组件或与其耦合的一些其它组件。 该命令可以被接收并且此后被执行。 响应可以在反馈路径上传送到CSP的第二部分。 可以由CSP接收和执行的非限制性示例性应用指令包括检查表面故障，陷阱，等待，信号，失速，翻转和触发。
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公开(公告)号：US20070115292A1
公开(公告)日：2007-05-24
申请号：US11552649
申请日：2006-10-25
申请人： John Brothers , Hsilin Huang , Boris Prokopenko
发明人： John Brothers , Hsilin Huang , Boris Prokopenko
IPC分类号： G06T1/20
CPC分类号： G06F9/542 , G06F9/3879 , G06F9/485 , G06F9/526 , G06T1/20
摘要： A GPU pipeline is synchronized by sending a fence command from a first module to an addressed synchronization register pair. Fence command associated data may be stored in a fence register of the addressed register pair. A second module sends a wait command with associated data to the addressed register pair, which may be compared to the data in the fence register. If the fence register data is greater than or equal to the wait command associated data, the second module may be acknowledged for sending the wait command and released for processing other graphics operations. If the fence register data is less than the wait command associated data, the second module is stalled until subsequent receipt of a fence command having data that is greater than or equal to the wait command associated data, which may be written to a wait register associated to the addressed register pair.
摘要翻译： 通过从第一模块发送fence命令到寻址的同步寄存器对来同步GPU流水线。 栅栏命令相关数据可以存储在寻址的寄存器对的栅栏寄存器中。 第二个模块发送一个具有关联数据的等待命令到寻址的寄存器对，这可以与围栏寄存器中的数据进行比较。 如果栅栏寄存器数据大于等于等待命令关联数据，则可以确认第二模块用于发送等待命令并被释放用于处理其他图形操作。 如果栅栏寄存器数据小于等待命令相关联的数据，则第二模块停止，直到后续接收到具有大于或等于等待命令关联数据的数据的围栏命令，该等待命令可被写入等待寄存器 到寻址寄存器对。
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3.发明申请公开(公告)号：US20070091102A1
公开(公告)日：2007-04-26
申请号：US11552693
申请日：2006-10-25
IPC分类号： G06T1/20
CPC分类号： G06F9/542 , G06F9/3879 , G06F9/485 , G06F9/526 , G06T1/20
摘要： A method for high level synchronization between an application and a graphics pipeline comprises receiving an application instruction in an input stream at a predetermined component, such as a command stream processor (CSP), as sent by a central processing unit. The CSP may have a first portion coupled to a next component in the graphics pipeline and a second portion coupled to a plurality of components of the graphics pipeline. A command associated with the application instruction may be forwarded from the first portion to the next component in the graphics pipeline or some other component coupled thereto. The command may be received and thereafter executed. A response may be communicated on a feedback path to the second portion of the CSP. Nonlimiting exemplary application instructions that may be received and executed by the CSP include check surface fault, trap, wait, signal, stall, flip, and trigger.
摘要翻译： 一种用于应用程序和图形流水线之间的高级别同步的方法包括：在由中央处理单元发送的诸如命令流处理器（CSP）的预定组件的输入流中接收应用程序指令。 CSP可以具有耦合到图形流水线中的下一个组件的第一部分和耦合到图形流水线的多个组件的第二部分。 与应用指令相关联的命令可以从第一部分转发到图形流水线中的下一个组件或与其耦合的一些其它组件。 该命令可以被接收并且此后被执行。 响应可以在反馈路径上传送到CSP的第二部分。 可以由CSP接收和执行的非限制性示例性应用指令包括检查表面故障，陷阱，等待，信号，失速，翻转和触发。
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公开(公告)号：US20070091101A1
公开(公告)日：2007-04-26
申请号：US11530052
申请日：2006-09-08
申请人： Hsilin Huang , Boris Prokopenko , John Brothers
发明人： Hsilin Huang , Boris Prokopenko , John Brothers
IPC分类号： G06T1/20
CPC分类号： G06F9/542 , G06F9/3879 , G06F9/485 , G06F9/526 , G06T1/20
摘要： A command parser in a GPU is configured to schedule execution of received commands and includes a first input coupled to a scheduler. The first command parser input is configured to communicate bus interface commands to the command parser for execution. A second command parser input is coupled to a controller that receives ring buffer commands from the scheduler in association with a new or previously-partially executed ring buffer, or context, which are executed by the command parser. A third command parser input coupled to a command DMA component that receives DMA commands from the controller that arc also contained in the new or previously-partially executed ring buffer, which are forwarded to the command parser for execution. The command parser forwards data corresponding to commands received on one or more the first, second, and third inputs via one or more outputs.
摘要翻译： GPU中的命令解析器被配置为调度所接收命令的执行，并且包括耦合到调度器的第一输入。 第一个命令解析器输入被配置为将总线接口命令传递给命令解析器以供执行。 第二命令解析器输入耦合到控制器，该控制器从由调度器接收环形缓冲器命令，与由命令解析器执行的新的或先前部分执行的环形缓冲器或上下文相关联。 第三个命令解析器输入耦合到命令DMA组件，该组件接收来自控制器的DMA命令，该命令也包含在新的或先前部分执行的环形缓冲器中，这些命令被转发到命令解析器以供执行。 命令解析器经由一个或多个输出转发对应于在一个或多个第一，第二和第三输入上接收的命令的数据。
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公开(公告)号：US08004533B2
公开(公告)日：2011-08-23
申请号：US11530052
申请日：2006-09-08
申请人： Hsilin Huang , Boris Prokopenko , John Brothers
发明人： Hsilin Huang , Boris Prokopenko , John Brothers
IPC分类号： G06T1/20
CPC分类号： G06F9/542 , G06F9/3879 , G06F9/485 , G06F9/526 , G06T1/20
摘要： A command parser in a GPU is configured to schedule execution of received commands and includes a first input coupled to a scheduler. The first command parser input is configured to communicate bus interface commands to the command parser for execution. A second command parser input is coupled to a controller that receives ring buffer commands from the scheduler in association with a new or previously-partially executed ring buffer, or context, which are executed by the command parser. A third command parser input coupled to a command DMA component that receives DMA commands from the controller that are also contained in the new or previously-partially executed ring buffer, which are forwarded to the command parser for execution. The command parser forwards data corresponding to commands received on one or more the first, second, and third inputs via one or more outputs.
摘要翻译： GPU中的命令解析器被配置为调度所接收命令的执行，并且包括耦合到调度器的第一输入。 第一个命令解析器输入被配置为将总线接口命令传递给命令解析器以供执行。 第二命令解析器输入耦合到控制器，该控制器从由调度器接收环形缓冲器命令，与由命令解析器执行的新的或先前部分执行的环形缓冲器或上下文相关联。 第三个命令解析器输入耦合到命令DMA组件，该组件接收来自控制器的DMA命令，该命令也包含在新的或先前部分执行的环形缓冲器中，这些命令被转发到命令解析器以供执行。 命令解析器经由一个或多个输出转发对应于在一个或多个第一，第二和第三输入上接收的命令的数据。
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公开(公告)号：US07755632B2
公开(公告)日：2010-07-13
申请号：US11552649
申请日：2006-10-25
申请人： John Brothers , Hsilin Huang , Boris Prokopenko
发明人： John Brothers , Hsilin Huang , Boris Prokopenko
IPC分类号： G06F13/00
CPC分类号： G06F9/542 , G06F9/3879 , G06F9/485 , G06F9/526 , G06T1/20
摘要： A GPU pipeline is synchronized by sending a fence command from a first module to an addressed synchronization register pair. Fence command associated data may be stored in a fence register of the addressed register pair. A second module sends a wait command with associated data to the addressed register pair, which may be compared to the data in the fence register. If the fence register data is greater than or equal to the wait command associated data, the second module may be acknowledged for sending the wait command and released for processing other graphics operations. If the fence register data is less than the wait command associated data, the second module is stalled until subsequent receipt of a fence command having data that is greater than or equal to the wait command associated data, which may be written to a wait register associated to the addressed register pair.
摘要翻译： 通过从第一模块发送fence命令到寻址的同步寄存器对来同步GPU流水线。 栅栏命令相关数据可以存储在寻址的寄存器对的栅栏寄存器中。 第二个模块发送一个具有关联数据的等待命令到寻址的寄存器对，这可以与围栏寄存器中的数据进行比较。 如果栅栏寄存器数据大于等于等待命令关联数据，则可以确认第二模块用于发送等待命令并被释放用于处理其他图形操作。 如果栅栏寄存器数据小于等待命令相关联的数据，则第二模块停止，直到后续接收到具有大于或等于等待命令关联数据的数据的围栏命令，该等待命令可被写入等待寄存器 到寻址寄存器对。
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7.发明授权公开(公告)号：US07030878B2
公开(公告)日：2006-04-18
申请号：US10804862
申请日：2004-03-19
申请人： Jiangming Xu , Wen-Chung Chen , Yuanfeng Wang , Liang Li , John Brothers , Boris Prokopenko
发明人： Jiangming Xu , Wen-Chung Chen , Yuanfeng Wang , Liang Li , John Brothers , Boris Prokopenko
CPC分类号： G06T15/60 , G06T15/005
摘要： The computer graphics system is configured to generate a shadow effect with a stencil shadow volume method using a combination of compressed and uncompressed stencil buffers in coordination with compressed and uncompressed depth data buffers. An uncompressed stencil buffer is capable of storing stencil shadow volume data for each pixel and a compressed stencil buffer is capable of storing stencil shadow volume data for a group of pixels.
摘要翻译： 计算机图形系统被配置为使用压缩和未压缩模板缓冲器的组合，使用压缩和未压缩的深度数据缓冲器来生成具有模板阴影卷方法的阴影效果。 未压缩的模板缓冲器能够存储每个像素的模板阴影体积数据，并且压缩模板缓冲器能够存储一组像素的模板阴影体积数据。
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公开(公告)号：US20060038822A1
公开(公告)日：2006-02-23
申请号：US10924068
申请日：2004-08-23
申请人： Jiangming Xu , Wen-Chung Chen , Yuanfeng Wang , Liang Li , John Brothers , Boris Prokopenko
发明人： Jiangming Xu , Wen-Chung Chen , Yuanfeng Wang , Liang Li , John Brothers , Boris Prokopenko
摘要： The computer graphics system is configured to improve the performance of a stencil shadow volume method for rendering shadows. The apparatus and methods utilize a combination of compressed and uncompressed stencil buffers in coordination with compressed and uncompressed depth data buffers. An uncompressed stencil buffer is capable of storing stencil shadow volume data for each pixel and a compressed stencil buffer is capable of storing stencil shadow volume data for a group of pixels. The compressed stencil buffer is utilized with a compressed stencil buffer cache to perform a stencil shadow volume operation more efficiently than present methods.
摘要翻译： 计算机图形系统被配置为提高用于渲染阴影的模板阴影卷方法的性能。 该装置和方法利用压缩和未压缩模板缓冲器的组合与压缩和未压缩的深度数据缓冲器协调。 未压缩的模板缓冲器能够存储每个像素的模板阴影体积数据，并且压缩模板缓冲器能够存储一组像素的模板阴影体积数据。 压缩模板缓冲器与压缩模板缓冲区缓存一起使用，以比当前方法更有效地执行模板阴影卷操作。
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公开(公告)号：US20100110089A1
公开(公告)日：2010-05-06
申请号：US12266115
申请日：2008-11-06
IPC分类号： G06T1/00
CPC分类号： G06T1/20
摘要： Included are systems and methods for Graphics Processing Unit (GPU) synchronization. At least one embodiment of a system includes at least one producer GPU configured to receive data related to at least one context, the at least one producer GPU further configured to process at least a portion of the received data. Some embodiments include at least one consumer GPU configured to received data from the producer GPU, the consumer GPU further configured to stall execution of the received data until a fence value is received.
摘要翻译： 包括用于图形处理单元（GPU）同步的系统和方法。 系统的至少一个实施例包括被配置为接收与至少一个上下文相关的数据的至少一个生成器GPU，所述至少一个生成器GPU还被配置为处理所接收的数据的至少一部分。 一些实施例包括被配置为从生成器GPU接收数据的至少一个消费者GPU，消费者GPU还被配置为停止所接收的数据的执行，直到接收到围栏值。
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10.发明授权Metaprocessor for GPU control and synchronization in a multiprocessor environment 有权用于多处理器环境中GPU控制和同步的元处理器公开(公告)号：US08368701B2
公开(公告)日：2013-02-05
申请号：US12266034
申请日：2008-11-06
CPC分类号： G06T1/20 , G06F9/30072 , G06F9/30094 , G06F9/3867 , G06F9/3877 , G06F9/3885 , G06F9/3897 , G06F13/14 , G06F15/7867
摘要： Included are embodiments of systems and methods for processing metacommands. In at least one exemplary embodiment a Graphics Processing Unit (GPU) includes a metaprocessor configured to process at least one context register, the metaprocessor including context management logic and a metaprocessor control register block coupled to the metaprocessor, the metaprocessor control register block configured to receive metaprocessor configuration data, the metaprocessor control register block further configured to define metacommand execution logic block behavior. Some embodiments include a Bus Interface Unit (BIU) configured to provide the access from a system processor to the metaprocessor and a GPU command stream processor configured to fetch a current context command stream and send commands for execution to a GPU pipeline and metaprocessor.
摘要翻译： 包括用于处理元命令的系统和方法的实施例。 在至少一个示例性实施例中，图形处理单元（GPU）包括配置成处理至少一个上下文寄存器的元处理器，所述元处理器包括上下文管理逻辑和耦合到元处理器的元处理器控制寄存器块，所述元处理器控制寄存器块被配置为接收 元处理器配置数据，元处理器控制寄存器块进一步配置为定义metacommand执行逻辑块行为。 一些实施例包括被配置为提供从系统处理器到元处理器的访问的总线接口单元（BIU）以及被配置为获取当前上下文命令流并且发送用于执行到GPU流水线和元处理器的命令的GPU命令流处理器。
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