Optional color space conversion
    1.
    发明授权
    Optional color space conversion 有权
    可选颜色空间转换

    公开(公告)号:US07593021B1

    公开(公告)日:2009-09-22

    申请号:US10939624

    申请日:2004-09-13

    IPC分类号: G09G5/02

    摘要: An apparatus and method for converting color data from one color space to another color space. A driver determines that a set of shader program instructions perform a color conversion function and the set of shader program instructions are replaced with either a single shader program instruction or a flag is set within an existing shader program instruction to specify that output color data is represented in a nonlinear color format. The output color data is converted to the nonlinear color format prior to being stored in a frame buffer. Nonlinear color data read from the frame buffer is converted to a linear color format prior to shading, blending, or raster operations.

    摘要翻译: 一种用于将颜色数据从一个颜色空间转换为另一个颜色空间的装置和方法。 驱动程序确定一组着色器程序指令执行颜色转换功能,并且一组着色器程序指令将被替换为单个着色器程序指令,或者在现有着色器程序指令中设置一个标志,以指定输出颜色数据被表示 以非线性颜色格式。 在存储在帧缓冲器中之前,将输出颜色数据转换为非线性颜色格式。 在阴影,混合或光栅操作之前,从帧缓冲区读取的非线性颜色数据被转换为线性颜色格式。

    Optional color space conversion
    2.
    发明授权
    Optional color space conversion 有权
    可选颜色空间转换

    公开(公告)号:US07973802B1

    公开(公告)日:2011-07-05

    申请号:US11956298

    申请日:2007-12-13

    IPC分类号: G09G5/02

    摘要: An apparatus and method for converting color data from one color space to another color space. A driver determines that a set of shader program instructions perform a color conversion function and the set of shader program instructions are replaced with either a single shader program instruction or a flag is set within an existing shader program instruction to specify that output color data is represented in a nonlinear color format. The output color data is converted to the nonlinear color format prior to being stored in a frame buffer. Nonlinear color data read from the frame buffer is converted to a linear color format prior to shading, blending, or raster operations.

    摘要翻译: 一种用于将颜色数据从一个颜色空间转换为另一个颜色空间的装置和方法。 驱动程序确定一组着色器程序指令执行颜色转换功能,并且一组着色器程序指令将被替换为单个着色器程序指令,或者在现有着色器程序指令中设置一个标志,以指定输出颜色数据被表示 以非线性颜色格式。 在存储在帧缓冲器中之前,将输出颜色数据转换为非线性颜色格式。 在阴影,混合或光栅操作之前,从帧缓冲区读取的非线性颜色数据被转换为线性颜色格式。

    Content addressable memory with an internally-timed write operation
    3.
    发明授权
    Content addressable memory with an internally-timed write operation 有权
    内部可寻址存储器,具有内部定时的写操作

    公开(公告)号:US06230237B1

    公开(公告)日:2001-05-08

    申请号:US09150513

    申请日:1998-09-09

    IPC分类号: G06F1202

    CPC分类号: G06F12/1027 G11C15/00

    摘要: A content addressable memory with an internally-timed write operation includes a data input for receiving a input word. Coupled to the data input are a plurality of storage registers comprising stored words. Each storage register includes a comparison circuit for comparing the stored word with the input word and producing therefrom a match output indicating a match when the stored word matches the input word, and indicating a miss when the stored word does not match the input word. Coupled to the storage registers is a miss detector for generating a miss signal responsive to each of the match outputs of the storage registers indicating a miss. Coupled to the miss detector is a write cycle circuit for writing the input word to at least one of the storage registers responsive to receiving the miss signal.

    摘要翻译: 具有内部定时写入操作的内容可寻址存储器包括用于接收输入字的数据输入。 耦合到数据输入的是包括存储字的多个存储寄存器。 每个存储寄存器包括比较电路,用于将存储的字与输入字进行比较,从而产生指示所存储的字与输入字匹配时的匹配的匹配输出,并且当所存储的字与输入字不匹配时指示未命中。 耦合到存储寄存器的是错误检测器,用于响应于存储寄存器中的每个匹配输出而产生未命中信号,指示未命中。 耦合到未命中检测器是用于响应于接收到未命中信号而将输入字写入至少一个存储寄存器的写周期电路。

    Buffering unit to support graphics processing operations
    5.
    发明授权
    Buffering unit to support graphics processing operations 有权
    缓冲单元支持图形处理操作

    公开(公告)号:US08139071B1

    公开(公告)日:2012-03-20

    申请号:US11556021

    申请日:2006-11-02

    IPC分类号: G06T1/60

    CPC分类号: G06T1/60

    摘要: An apparatus and method for buffering graphics data are described. In one embodiment, a graphics processing apparatus includes a storage unit and a reorder control unit that is connected to the storage unit. The reorder control unit is configured to coordinate storage of vertex attributes in the storage unit so as to convert the vertex attributes from an initial order to a modified order. The reorder control unit is configured to identify a subset of the vertex attributes to be stored within a common range of addresses in the storage unit, and the reorder control unit is configured to access the storage unit such that the subset of the vertex attributes is written into the storage unit substantially in parallel.

    摘要翻译: 描述用于缓冲图形数据的装置和方法。 在一个实施例中,图形处理装置包括连接到存储单元的存储单元和重新排序控制单元。 重新排序控制单元被配置为协调存储单元中的顶点属性的存储,以便将顶点属性从初始顺序转换为修改顺序。 重排序控制单元被配置为识别要存储在存储单元中的公共地址范围内的顶点属性的子集,并且重新排序控制单元被配置为访问存储单元,使得顶点属性的子集被写入 基本上并行地进入存储单元。

    Using scan chains for context switching
    6.
    发明授权
    Using scan chains for context switching 有权
    使用扫描链进行上下文切换

    公开(公告)号:US08056088B1

    公开(公告)日:2011-11-08

    申请号:US11301517

    申请日:2005-12-13

    摘要: The invention sets forth an approach to context switching that utilizes scan chains modified to perform context switching operations. The design requires substantially less additional silicon area and design engineering effort than existing context switch approaches, while operating substantially faster and providing additional debug observability during context switching operations.

    摘要翻译: 本发明提出了利用被修改以执行上下文切换操作的扫描链的上下文切换的方法。 与现有的上下文切换方法相比,该设计需要比现有的上下文切换方法少得多的额外的硅面积和设计工程设计,同时在上下文切换操作期间显着更快地运行并提

    Clipping graphics primitives to the w=0 plane
    7.
    发明授权
    Clipping graphics primitives to the w=0 plane 有权
    将图形原语剪切到w = 0平面

    公开(公告)号:US07466322B1

    公开(公告)日:2008-12-16

    申请号:US11195389

    申请日:2005-08-02

    IPC分类号: G09G5/00

    CPC分类号: G06T11/40

    摘要: Vertices defining a graphics primitive are converted into homogeneous space and clipped against a single clipping plane, the w=0 plane, to produce a clipped graphics primitive having vertices including w coordinates that are greater than or equal to zero. Rasterizing a graphics primitive having a vertex with a w coordinates that is greater than or equal to zero is less complex than rasterizing a graphics primitive having a vertex with a w coordinate that is less than zero. Clipping against the w=0 plane is less complex than conventional clipping since conventional clipping may require that the graphics primitive be clipped against each of the six faces of the viewing frustum to produce a clipped graphics primitive.

    摘要翻译: 定义图形基元的顶点被转换成均匀空间,并且相对于单个剪切平面(w = 0平面)被剪切,以产生具有包括大于或等于零的w坐标的顶点的剪切图形基元。 栅格化具有w坐标大于或等于零的顶点的图形原语比光栅化具有小于零的w坐标的顶点的图形基元复杂化。 针对w = 0平面的剪切不如传统的剪裁那样复杂,因为常规的剪裁可能要求将图形原语对准观察平截头体的六个面中的每一个以产生剪切的图形原语。

    Apparatus, system, and method for clipping graphics primitives with reduced sensitivity to vertex ordering
    8.
    发明授权
    Apparatus, system, and method for clipping graphics primitives with reduced sensitivity to vertex ordering 有权
    用于削减对顶点排序灵敏度降低的图形图元的装置,系统和方法

    公开(公告)号:US07292254B1

    公开(公告)日:2007-11-06

    申请号:US11294791

    申请日:2005-12-05

    IPC分类号: G09G5/00 G06T1/00

    CPC分类号: G06T15/30

    摘要: Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a mapping unit and a clipping engine that is connected to the mapping unit. The mapping unit is configured to map a graphics primitive onto a canonical representation. The clipping engine is configured to perform a set of clipping operations with respect to the canonical representation.

    摘要翻译: 描述用于剪切图形基元的装置,系统和方法。 在一个实施例中,图形处理装置包括连接到映射单元的映射单元和剪辑引擎。 映射单元被配置为将图形原语映射到规范表示。 剪辑引擎被配置为执行关于规范表示的一组剪切操作。

    Configurable output buffer ganging for a parallel processor
    10.
    发明授权
    Configurable output buffer ganging for a parallel processor 有权
    可配置的输出缓冲器组合用于并行处理器

    公开(公告)号:US07747842B1

    公开(公告)日:2010-06-29

    申请号:US11311993

    申请日:2005-12-19

    IPC分类号: G06F9/50

    CPC分类号: G06F9/5011

    摘要: An output buffer in a multi-threaded processor is managed to store a variable amount of output data. Parallel threads produce a variable amount of output data. A controller is configured to determine how much output buffer space is needed per thread and how many threads can execute in parallel, given the available space in the output buffer. The controller also determines where each thread writes to in the output buffer.

    摘要翻译: 管理多线程处理器中的输出缓冲器以存储可变量的输出数据。 并行线程产生可变量的输出数据。 控制器被配置为确定在输出缓冲区中可用空间的情况下,每个线程需要多少输出缓冲区空间以及并行执行多少个线程。 控制器还确定每个线程在输出缓冲区中写入的位置。