公开(公告)号：US06529402B1

公开(公告)日：2003-03-04

申请号：US10094533

申请日：2002-03-08

申请人： John E. Andersen ,  Louis Lu-Chen Hsu ,  Li-Kong Wang

发明人： John E. Andersen ,  Louis Lu-Chen Hsu ,  Li-Kong Wang

IPC分类号： G11C1100

CPC分类号： G11C11/417 ,  G11C5/025 ,  G11C8/08

摘要： A stacked block array architecture.for a SRAM memory for low power applications. The architecture turns on only the required data cells and sensing circuitry to access a particular set of data cells of interest. The wordline delay is reduced by using a shorter and wider wordline wire size. Although less power is consumed, the performance is improved by the reduction in loading of wordlines and bitlines.

摘要翻译： 堆叠块阵列架构，用于低功耗应用的SRAM存储器。 该架构仅打开所需的数据单元和感测电路以访问感兴趣的特定数据单元组。 通过使用更短和更宽的字线大小减小字线延迟。 虽然功耗较低，但通过减少字线和位线的负载来提高性能。

公开(公告)号：US06504777B1

公开(公告)日：2003-01-07

申请号：US09924661

申请日：2001-08-08

申请人： Louis Lu-Chen Hsu ,  Li-Kong Wang

发明人： Louis Lu-Chen Hsu ,  Li-Kong Wang

IPC分类号： G11C700

CPC分类号： G11C7/12 ,  G11C11/4094

摘要： In a high density dynamic memory circuit, the sense amplifiers are shared by several bitlines in order to maintain a high density and low power design. However, the bitline equalization level drifts after several cycles of operation, caused by an unbalanced capacitance resulting from a size difference of n-FET and p-FET latches in the sense amplifiers. An extra compensating capacitance Ce is added to the NCS node to adjust the loading capacitance to eliminate the bitline drifting.

摘要翻译： 在高密度动态存储器电路中，读出放大器由几个位线共享，以保持高密度和低功率设计。 然而，由于读出放大器中的n-FET和p-FET锁存器的大小差异导致的不平衡电容引起了几个周期的操作之后，位线均衡电平漂移。 一个额外的补偿电容Ce被添加到NCS节点以调整负载电容以消除位线漂移。

公开(公告)号：US06823293B2

公开(公告)日：2004-11-23

申请号：US10334312

申请日：2002-12-31

申请人： Howard H. Chen ,  Louis Lu-Chen Hsu ,  Brian L. Ji ,  Li-Kong Wang

发明人： Howard H. Chen ,  Louis Lu-Chen Hsu ,  Brian L. Ji ,  Li-Kong Wang

IPC分类号： G06F1500

CPC分类号： G01R31/3004 ,  G01R31/31721

摘要： A hierarchical power supply noise monitoring device and system for very large scale integrated circuits. The noise-monitoring device is fabricated on-chip to measure the noise on the chip. The noise-monitoring system includes a plurality of on-chip noise-monitoring devices distributed strategically across the chip. A noise-analysis algorithm analyzes the noise characteristics from the noise data collected from the noise-monitoring devices, and a hierarchical noise-monitoring system maps the noise of each core to the system on chip.

摘要翻译： 一种用于大规模集成电路的分层电源噪声监测装置和系统。 噪声监测装置是片上制造的，以测量芯片上的噪声。 噪声监测系统包括跨芯片战略性分布的多个片上噪声监测装置。 噪声分析算法从噪声监测装置收集的噪声数据中分析噪声特性，分层噪声监测系统将每个核心的噪声映射到片上系统。

公开(公告)号：US06426903B1

公开(公告)日：2002-07-30

申请号：US09923721

申请日：2001-08-07

申请人： Lawrence A. Clevenger ,  Louis Lu-Chen Hsu ,  Li-Kong Wang ,  Keith Kwong-Hon Wong

发明人： Lawrence A. Clevenger ,  Louis Lu-Chen Hsu ,  Li-Kong Wang ,  Keith Kwong-Hon Wong

IPC分类号： G11C700

CPC分类号： G11C29/80 ,  Y10S977/888 ,  Y10S977/943

摘要： A static redundancy arrangement for a circuit using a focused ion beam anti-fuse methodology which reduces the circuit layout area and the switching activity compared to a prior art dynamic redundancy scheme, resulting in less power, a simpler design and higher speed. Focused ion beam anti-fuse methodology is used to program redundancy for circuits, particularly wide I/O embedded DRAM macros. An anti-fuse array circuit is comprised of a plurality of anti-fuse programming elements, each of which comprises a latch circuit controlled by a set input signal, and an anti-fuse device which is programmed by a focused ion beam.

摘要翻译： 使用聚焦离子束反熔丝方法的电路的静态冗余布置，与现有技术的动态冗余方案相比，其减小了电路布局面积和开关活动，导致较少的功率，更简单的设计和更高的速度。 聚焦离子束反熔丝方法用于编程电路冗余，特别是宽I / O嵌入式DRAM宏。 反熔丝阵列电路由多个反熔丝编程元件组成，每个反熔丝编程元件包括由设定的输入信号控制的锁存电路和由聚焦离子束编程的反熔丝器件。

公开(公告)号：US06603690B1

公开(公告)日：2003-08-05

申请号：US10091663

申请日：2002-03-06

申请人： Howard Hao Chen ,  Louis Lu-Chen Hsu ,  Li-Kong Wang

发明人： Howard Hao Chen ,  Louis Lu-Chen Hsu ,  Li-Kong Wang

IPC分类号： G11C700

CPC分类号： G11C29/802

摘要： A static column redundancy scheme for a semiconductor memory such as an eDRAM. By utilizing the existing scan registers for SRAM array testing, the column redundancy information of each bank or each microcell of the memory chip can be scanned, stored and programmed during the power-on period. Two programming methods are disclosed to find the column redundancy information on the fly. In the first method, the column redundancy information is first stored in the SRAM, and is then written into the program registers of the corresponding bank or microcell location. In the second method, the column redundancy information is loaded directly into the program registers of a bank or microcell location according to the bank address information without loading the SRAM. Since the new static column redundancy scheme does not need to compare the incoming addresses, it eliminates the use of control and decoding circuits, which significantly reduces the power consumption for memory macros.

摘要翻译： 用于诸如eDRAM的半导体存储器的静态列冗余方案。 通过利用现有的扫描寄存器进行SRAM阵列测试，可以在上电期间扫描，存储和编程存储器芯片的每个存储体或每个微单元的列冗余信息。 公开了两种编程方法来即时查找列冗余信息。 在第一种方法中，列冗余信息首先存储在SRAM中，然后被写入对应的存储体或微小区位置的程序寄存器中。 在第二种方法中，列冗余信息根据存储体地址信息被直接加载到存储体或微小区位置的程序寄存器中而不加载SRAM。 由于新的静态列冗余方案不需要比较输入地址，因此无需使用控制和解码电路，这显着降低了存储宏的功耗。

公开(公告)号：US06504173B2

公开(公告)日：2003-01-07

申请号：US09757153

申请日：2001-01-09

申请人： Louis Lu-Chen Hsu ,  Li-Kong Wang

发明人： Louis Lu-Chen Hsu ,  Li-Kong Wang

IPC分类号： H01L3300

CPC分类号： H01L29/66772 ,  H01L29/78648

摘要： The present invention is directed to a method of fabricating a dual gate structure for use in FET devices wherein the dual gate structure comprises a bottom gate that is substantially a mirror image of the top gate. The method utilizes a shallow trench isolation process for the purpose of planarization and gate alignment. Also disclosed is a dual gate structure which is fabricated utilizing the method of the present invention.

摘要翻译： 本发明涉及一种制造用于FET器件的双栅极结构的方法，其中双栅结构包括基本上是顶栅的镜像的底栅。 该方法利用浅沟槽隔离工艺，用于平坦化和栅极对准。 还公开了利用本发明的方法制造的双栅结构。

公开(公告)号：US06207530B1

公开(公告)日：2001-03-27

申请号：US09100900

申请日：1998-06-19

申请人： Louis Lu-Chen Hsu ,  Li-Kong Wang

发明人： Louis Lu-Chen Hsu ,  Li-Kong Wang

IPC分类号： H01L2176

CPC分类号： H01L29/66772 ,  H01L29/78648

摘要： The present invention is directed to a method of fabricating a dual gate structure for use in FET devices wherein the dual gate structure comprises a bottom gate that is substantially a mirror image of the top gate. The method utilizes a shallow trench isolation process for the purpose of planarization and gate alignment. Also disclosed is a dual gate structure which is fabricated utilizing the method of the present invention.

摘要翻译： 本发明涉及一种制造用于FET器件的双栅极结构的方法，其中双栅结构包括基本上是顶栅的镜像的底栅。 该方法利用浅沟槽隔离工艺，用于平坦化和栅极对准。 还公开了利用本发明的方法制造的双栅结构。

公开(公告)号：US06307805B1

公开(公告)日：2001-10-23

申请号：US09745227

申请日：2000-12-21

申请人： John E. Andersen ,  Terence B. Hook ,  Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

发明人： John E. Andersen ,  Terence B. Hook ,  Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

IPC分类号： G11C700

CPC分类号： G11C8/08 ,  G11C11/418 ,  H01L27/11

摘要： A semiconductor memory device accessed with wordlines and bitlines has memory cells which operate at high performance with lower power consumption and have a high density. Each of the memory cells has pass transistors connected to a corresponding wordline and a corresponding pair of bitlines, and the pass transistors are gated by a signal of the corresponding wordline. The semiconductor memory device includes a wordline drive unit for selectively driving the wordlines in response to a row address. A wordline driver in the wordline drive unit boosts a corresponding wordline in a positive direction when the corresponding wordline is activated to access the memory cell and boosts the corresponding wordline in a negative direction when the corresponding wordline is inactive. By boosting the wordline in the positive direction, the performance of the memory cells is enhanced, and by boosting the wordline in the negative direction, a leakage current in the pass transistors with a low-threshold voltage is prevented.

摘要翻译： 用字线和位线访问的半导体存储器件具有以较低的功耗以高密度工作的高性能的存储单元。 每个存储单元具有连接到相应字线和相应的一对位线的传输晶体管，并且通过晶体管由相应字线的信号选通。 半导体存储器件包括用于响应于行地址选择性地驱动字线的字线驱动单元。 当对应的字线不活动时，字线驱动单元中的字线驱动器在相应的字线被激活以访问存储器单元并且在相反的方向上升高相应的字线时以正方向提升相应的字线。 通过在正方向上升压字线，增强了存储单元的性能，并且通过在负方向上升高字线，防止具有低阈值电压的通过晶体管中的漏电流。

公开(公告)号：US06434076B1

公开(公告)日：2002-08-13

申请号：US09766799

申请日：2001-01-22

申请人： John E. Andersen ,  Louis L. Hsu ,  Stephen Kosonocky ,  Li-Kong Wang

发明人： John E. Andersen ,  Louis L. Hsu ,  Stephen Kosonocky ,  Li-Kong Wang

IPC分类号： G11C800

CPC分类号： G11C7/1072 ,  G11C11/406

摘要： A power management circuit for an SRAM system including one or more isolated memory arrays and implementing a power source including a local power supply associated with each memory array and an external power supply connected to local supplies during an active mode of operation. The power management circuit comprises: a switch mechanism for disconnecting the external power supply to each of local power supply during a low power mode of operation; and, a refresh timing circuit implementing memory array refresh operation by selectively connecting the external power supply to a respective local power supply during the low power mode. During the low power mode, the refresh circuit intentionally enables the local power supply to float and allow it to drift to a lower predetermined voltage level prior to the memory array refresh operation.

摘要翻译： 一种用于SRAM系统的电源管理电路，包括一个或多个隔离存储器阵列，并且在主动操作模式期间实现包括与每个存储器阵列相关联的本地电源的电源和连接到本地电源的外部电源。 电源管理电路包括：开关机构，用于在低功率操作模式期间断开外部电源到每个本地电源; 以及通过在低功率模式期间选择性地将外部电源连接到各个本地电源来实现存储器阵列刷新操作的刷新定时电路。 在低功率模式期间，刷新电路有意地使本地电源浮动并允许其在存储器阵列刷新操作之前漂移到较低的预定电压电平。

公开(公告)号：US07447273B2

公开(公告)日：2008-11-04

申请号：US10708240

申请日：2004-02-18

申请人： Louis L. Hsu ,  Carl Radens ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Carl Radens ,  Li-Kong Wang

IPC分类号： H01L21/82 ,  H01P1/10

CPC分类号： H04L1/22 ,  H04L25/029 ,  H04L25/08

摘要： An integrated circuit is provided having a plurality of data transmitters, including a plurality of default data transmitters for transmitting data from a plurality of data sources and at least one redundancy data transmitter. A plurality of connection elements are provided having a first, low impedance connecting state and having a second, high impedance, disconnecting state. The connection elements are operable to disconnect a failing data transmitter from a corresponding output signal line and to connect the redundancy data transmitter to that output signal line in place of the failing data transmitter. In one preferred form, the connection elements include a fuse and an antifuse. In another form, the connection elements include micro-electromechanical (MEM) switches. The connecting elements preferably present the low impedance connecting state at frequencies which include signal switching frequencies above about 500 MHz.

摘要翻译： 提供了具有多个数据发送器的集成电路，包括用于从多个数据源发送数据的多个默认数据发送器和至少一个冗余数据发送器。 提供了具有第一低阻抗连接状态并且具有第二高阻抗断开状态的多个连接元件。 连接元件可操作以将故障数据发射器与相应的输出信号线断开连接，并将冗余数据发射器连接到该输出信号线来代替故障数据发射器。 在一个优选形式中，连接元件包括保险丝和反熔丝。 在另一种形式中，连接元件包括微机电（MEM）开关。 连接元件优选地在包括高于约500MHz的信号切换频率的频率处呈现低阻抗连接状态。