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1.发明授权Hierarchical power supply noise monitoring device and system for very large scale integrated circuits 有权用于大型集成电路的分层电源噪声监测装置和系统公开(公告)号：US06823293B2
公开(公告)日：2004-11-23
申请号：US10334312
申请日：2002-12-31
申请人： Howard H. Chen , Louis Lu-Chen Hsu , Brian L. Ji , Li-Kong Wang
发明人： Howard H. Chen , Louis Lu-Chen Hsu , Brian L. Ji , Li-Kong Wang
IPC分类号： G06F1500
CPC分类号： G01R31/3004 , G01R31/31721
摘要： A hierarchical power supply noise monitoring device and system for very large scale integrated circuits. The noise-monitoring device is fabricated on-chip to measure the noise on the chip. The noise-monitoring system includes a plurality of on-chip noise-monitoring devices distributed strategically across the chip. A noise-analysis algorithm analyzes the noise characteristics from the noise data collected from the noise-monitoring devices, and a hierarchical noise-monitoring system maps the noise of each core to the system on chip.
摘要翻译： 一种用于大规模集成电路的分层电源噪声监测装置和系统。 噪声监测装置是片上制造的，以测量芯片上的噪声。 噪声监测系统包括跨芯片战略性分布的多个片上噪声监测装置。 噪声分析算法从噪声监测装置收集的噪声数据中分析噪声特性，分层噪声监测系统将每个核心的噪声映射到片上系统。
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公开(公告)号：US06504777B1
公开(公告)日：2003-01-07
申请号：US09924661
申请日：2001-08-08
申请人： Louis Lu-Chen Hsu , Li-Kong Wang
发明人： Louis Lu-Chen Hsu , Li-Kong Wang
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C11/4094
摘要： In a high density dynamic memory circuit, the sense amplifiers are shared by several bitlines in order to maintain a high density and low power design. However, the bitline equalization level drifts after several cycles of operation, caused by an unbalanced capacitance resulting from a size difference of n-FET and p-FET latches in the sense amplifiers. An extra compensating capacitance Ce is added to the NCS node to adjust the loading capacitance to eliminate the bitline drifting.
摘要翻译： 在高密度动态存储器电路中，读出放大器由几个位线共享，以保持高密度和低功率设计。 然而，由于读出放大器中的n-FET和p-FET锁存器的大小差异导致的不平衡电容引起了几个周期的操作之后，位线均衡电平漂移。 一个额外的补偿电容Ce被添加到NCS节点以调整负载电容以消除位线漂移。
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公开(公告)号：US06426903B1
公开(公告)日：2002-07-30
申请号：US09923721
申请日：2001-08-07
IPC分类号： G11C700
CPC分类号： G11C29/80 , Y10S977/888 , Y10S977/943
摘要： A static redundancy arrangement for a circuit using a focused ion beam anti-fuse methodology which reduces the circuit layout area and the switching activity compared to a prior art dynamic redundancy scheme, resulting in less power, a simpler design and higher speed. Focused ion beam anti-fuse methodology is used to program redundancy for circuits, particularly wide I/O embedded DRAM macros. An anti-fuse array circuit is comprised of a plurality of anti-fuse programming elements, each of which comprises a latch circuit controlled by a set input signal, and an anti-fuse device which is programmed by a focused ion beam.
摘要翻译： 使用聚焦离子束反熔丝方法的电路的静态冗余布置，与现有技术的动态冗余方案相比，其减小了电路布局面积和开关活动，导致较少的功率，更简单的设计和更高的速度。 聚焦离子束反熔丝方法用于编程电路冗余，特别是宽I / O嵌入式DRAM宏。 反熔丝阵列电路由多个反熔丝编程元件组成，每个反熔丝编程元件包括由设定的输入信号控制的锁存电路和由聚焦离子束编程的反熔丝器件。
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公开(公告)号：US06529402B1
公开(公告)日：2003-03-04
申请号：US10094533
申请日：2002-03-08
IPC分类号： G11C1100
CPC分类号： G11C11/417 , G11C5/025 , G11C8/08
摘要： A stacked block array architecture.for a SRAM memory for low power applications. The architecture turns on only the required data cells and sensing circuitry to access a particular set of data cells of interest. The wordline delay is reduced by using a shorter and wider wordline wire size. Although less power is consumed, the performance is improved by the reduction in loading of wordlines and bitlines.
摘要翻译： 堆叠块阵列架构，用于低功耗应用的SRAM存储器。 该架构仅打开所需的数据单元和感测电路以访问感兴趣的特定数据单元组。 通过使用更短和更宽的字线大小减小字线延迟。 虽然功耗较低，但通过减少字线和位线的负载来提高性能。
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公开(公告)号：US06603690B1
公开(公告)日：2003-08-05
申请号：US10091663
申请日：2002-03-06
申请人： Howard Hao Chen , Louis Lu-Chen Hsu , Li-Kong Wang
发明人： Howard Hao Chen , Louis Lu-Chen Hsu , Li-Kong Wang
IPC分类号： G11C700
CPC分类号： G11C29/802
摘要： A static column redundancy scheme for a semiconductor memory such as an eDRAM. By utilizing the existing scan registers for SRAM array testing, the column redundancy information of each bank or each microcell of the memory chip can be scanned, stored and programmed during the power-on period. Two programming methods are disclosed to find the column redundancy information on the fly. In the first method, the column redundancy information is first stored in the SRAM, and is then written into the program registers of the corresponding bank or microcell location. In the second method, the column redundancy information is loaded directly into the program registers of a bank or microcell location according to the bank address information without loading the SRAM. Since the new static column redundancy scheme does not need to compare the incoming addresses, it eliminates the use of control and decoding circuits, which significantly reduces the power consumption for memory macros.
摘要翻译： 用于诸如eDRAM的半导体存储器的静态列冗余方案。 通过利用现有的扫描寄存器进行SRAM阵列测试，可以在上电期间扫描，存储和编程存储器芯片的每个存储体或每个微单元的列冗余信息。 公开了两种编程方法来即时查找列冗余信息。 在第一种方法中，列冗余信息首先存储在SRAM中，然后被写入对应的存储体或微小区位置的程序寄存器中。 在第二种方法中，列冗余信息根据存储体地址信息被直接加载到存储体或微小区位置的程序寄存器中而不加载SRAM。 由于新的静态列冗余方案不需要比较输入地址，因此无需使用控制和解码电路，这显着降低了存储宏的功耗。
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公开(公告)号：US06504173B2
公开(公告)日：2003-01-07
申请号：US09757153
申请日：2001-01-09
申请人： Louis Lu-Chen Hsu , Li-Kong Wang
发明人： Louis Lu-Chen Hsu , Li-Kong Wang
IPC分类号： H01L3300
CPC分类号： H01L29/66772 , H01L29/78648
摘要： The present invention is directed to a method of fabricating a dual gate structure for use in FET devices wherein the dual gate structure comprises a bottom gate that is substantially a mirror image of the top gate. The method utilizes a shallow trench isolation process for the purpose of planarization and gate alignment. Also disclosed is a dual gate structure which is fabricated utilizing the method of the present invention.
摘要翻译： 本发明涉及一种制造用于FET器件的双栅极结构的方法，其中双栅结构包括基本上是顶栅的镜像的底栅。 该方法利用浅沟槽隔离工艺，用于平坦化和栅极对准。 还公开了利用本发明的方法制造的双栅结构。
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公开(公告)号：US06207530B1
公开(公告)日：2001-03-27
申请号：US09100900
申请日：1998-06-19
申请人： Louis Lu-Chen Hsu , Li-Kong Wang
发明人： Louis Lu-Chen Hsu , Li-Kong Wang
IPC分类号： H01L2176
CPC分类号： H01L29/66772 , H01L29/78648
摘要： The present invention is directed to a method of fabricating a dual gate structure for use in FET devices wherein the dual gate structure comprises a bottom gate that is substantially a mirror image of the top gate. The method utilizes a shallow trench isolation process for the purpose of planarization and gate alignment. Also disclosed is a dual gate structure which is fabricated utilizing the method of the present invention.
摘要翻译： 本发明涉及一种制造用于FET器件的双栅极结构的方法，其中双栅结构包括基本上是顶栅的镜像的底栅。 该方法利用浅沟槽隔离工艺，用于平坦化和栅极对准。 还公开了利用本发明的方法制造的双栅结构。
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公开(公告)号：US20120248567A1
公开(公告)日：2012-10-04
申请号：US13494327
申请日：2012-06-12
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/76807 , H01L21/76892 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A structure. The structure includes: a substrate, a first electrode in the substrate, first dielectric layer above both the substrate and the first electrode, a second dielectric layer above the first dielectric layer, and a fuse element buried in the first dielectric layer. The first electrode includes a first electrically conductive material. A top surface of the first dielectric layer is further from a top surface of the first electrode than is any other surface of the first dielectric layer. The first dielectric layer includes a first dielectric material and a second dielectric material. A bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer. The second dielectric layer includes the second dielectric material.
摘要翻译： 一个结构。 该结构包括：衬底，衬底中的第一电极，衬底和第一电极上的第一电介质层，第一电介质层上方的第二电介质层和埋在第一电介质层中的熔丝元件。 第一电极包括第一导电材料。 第一电介质层的顶表面比第一电介质层的任何其它表面更远离第一电极的顶表面。 第一电介质层包括第一电介质材料和第二电介质材料。 第二电介质层的底表面与第一电介质层的顶表面直接物理接触。 第二电介质层包括第二电介质材料。
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9.发明授权Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering 有权结合了具有减小的结电容和漏极引起的屏障降低的半导体器件结构公开(公告)号：US07984408B2
公开(公告)日：2011-07-19
申请号：US11875013
申请日：2007-10-19
CPC分类号： H01L29/78603 , G11C29/54 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/66636 , H01L29/66772
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconductor device structure of the design structure includes a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant.
摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括半导体器件结构，其特征在于结电容减小和漏极引起的栅极降低。 设计结构的半导体器件结构包括设置在半导体层和衬底之间的半导体层和介电层。 电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。
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公开(公告)号：US07968949B2
公开(公告)日：2011-06-28
申请号：US11668717
申请日：2007-01-30
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76829 , H01L21/76831 , H01L29/6653 , H01L29/78
摘要： Contact forming methods and a related semiconductor device are disclosed. One method includes forming a first liner over the structure and the substrate, the first liner covering sidewall of the structure; forming a dielectric layer over the first liner and the structure; forming a contact hole in the dielectric layer to the first liner; forming a second liner in the contact hole including over the first liner covering the sidewall; removing the first and second liners at a bottom of the contact hole; and filling the contact hole with a conductive material to form the contact. The thicker liner(s) over the sidewall of the structure prevents shorting, and allows for at least maintaining any intrinsic stress in one or more of the liner(s).
摘要翻译： 公开了触点形成方法和相关的半导体器件。 一种方法包括在结构和衬底上形成第一衬里，第一衬套覆盖结构的侧壁; 在所述第一衬垫和所述结构上形成介电层; 在所述介电层中形成与所述第一衬垫的接触孔; 在所述接触孔中形成第二衬垫，包括覆盖所述侧壁的所述第一衬套上方; 在接触孔的底部移除第一和第二衬垫; 并用导电材料填充接触孔以形成接触。 结构侧壁上较厚的衬套防止短路，并允许至少保持一个或多个衬套中的任何固有应力。
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