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    Metal-insulator-metal (MIM) capacitor with deep trench (DT) structure and method in a silicon-on-insulator (SOI)
    1.
    发明授权
    Metal-insulator-metal (MIM) capacitor with deep trench (DT) structure and method in a silicon-on-insulator (SOI) 有权
    具有深沟槽（DT）结构的金属绝缘体金属（MIM）电容器和绝缘体上硅（SOI）

    公开(公告)号：US08946045B2

    公开(公告)日：2015-02-03

    申请号：US13457601

    申请日：2012-04-27

    申请人： John E. Barth, Jr. ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson

    发明人： John E. Barth, Jr. ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L29/02

    CPC分类号： H01L28/40 ,  H01L21/84 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/66181 ,  H01L29/945

    摘要： A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.

    摘要翻译： 公开了形成金属 - 绝缘体 - 金属（MIM）沟槽电容器的结构。 该结构包括具有金属层和至少一个电介质层的多层基底。 沟槽被蚀刻到衬底中，穿过金属层。 沟槽衬有与金属层接触的金属材料，金属层包括电容器的第一节点。 电介质材料将沟槽中的金属材料排列。 沟槽填充有导体。 将金属材料排列的电介质材料将导体与金属层和衬套在沟槽上的金属材料分开。 导体包括电容器的第二节点。

    Semiconductor-on-oxide structure and method of forming
    5.
    发明授权
    Semiconductor-on-oxide structure and method of forming 有权
    半导体氧化物结构及其形成方法

    公开(公告)号：US08877603B2

    公开(公告)日：2014-11-04

    申请号：US13435056

    申请日：2012-03-30

    申请人： John E. Barth, Jr. ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson

    发明人： John E. Barth, Jr. ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson

    IPC分类号： H01L21/76 ,  H01L21/30 ,  H01L21/46

    CPC分类号： H01L29/06 ,  H01L21/76254

    摘要： Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.

    摘要翻译： 公开了形成这种结构的半导体 - 氧化物结构和相关方法。 在一种情况下，一种方法包括：在衬底上形成第一介质层; 在所述第一介电层上形成第一导电层，所述第一导电层包括金属或硅化物之一; 在所述第一导电层上形成第二电介质层; 将施主晶片键合到第二介电层，施主晶片包括施主电介质和半导体层; 切割施主晶片以去除施主半导体层的一部分; 从所述施主半导体层的未移动部分形成至少一个半导体隔离区; 以及通过施主电介质和第二介电层形成与第一导电层的接触。

    SEMICONDUCTOR-ON-OXIDE STRUCTURE AND METHOD OF FORMING
    6.
    发明申请
    SEMICONDUCTOR-ON-OXIDE STRUCTURE AND METHOD OF FORMING 有权
    半导体氧化物结构及其形成方法

    公开(公告)号：US20130256830A1

    公开(公告)日：2013-10-03

    申请号：US13435056

    申请日：2012-03-30

    申请人： John E. Barth, JR. ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson

    发明人： John E. Barth, JR. ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson

    IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L29/06 ,  H01L21/762

    CPC分类号： H01L29/06 ,  H01L21/76254

    摘要： Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.

    摘要翻译： 公开了形成这种结构的半导体 - 氧化物结构和相关方法。 在一种情况下，一种方法包括：在衬底上形成第一介质层; 在所述第一介电层上形成第一导电层，所述第一导电层包括金属或硅化物之一; 在所述第一导电层上形成第二电介质层; 将施主晶片键合到第二介电层，施主晶片包括施主电介质和半导体层; 切割施主晶片以去除施主半导体层的一部分; 从所述施主半导体层的未移动部分形成至少一个半导体隔离区; 以及通过施主电介质和第二介电层形成与第一导电层的接触。

    Method of forming a trench capacitor DRAM cell
    7.
    发明授权
    Method of forming a trench capacitor DRAM cell 失效
    形成沟槽电容器DRAM单元的方法

    公开(公告)号：US06340615B1

    公开(公告)日：2002-01-22

    申请号：US09466605

    申请日：1999-12-17

    申请人： Sundar K. Iyer ,  Rama Divakaruni ,  Herbert L. Ho ,  Subramanian Iyer ,  Babar A. Khan

    发明人： Sundar K. Iyer ,  Rama Divakaruni ,  Herbert L. Ho ,  Subramanian Iyer ,  Babar A. Khan

    IPC分类号： H01L218242

    CPC分类号： H01L27/10867

    摘要： A method of connecting a trench capacitor in a dynamic random access memory (DRAM) cell. First, trenches are formed in a silicon substrate using a masking layer including a pad nitride layer on a pad oxide layer. Trench capacitors are formed in the trenches. A buried strap is formed in each trench on the capacitor. The nitride pad layer is pulled back from the trench openings, exposing the pad oxide layer and any strap material that may have replaced the pad oxide layer around the trenches. The straps and trench sidewalls are doped to form a resistive connection. During a subsequent shallow trench isolation (STI) process, which involves an oxidation step, the exposed strap material on the surface of the silicon surface layer forms oxide unrestrained by pad nitride without stressing the silicon substrate.

    摘要翻译： 一种在动态随机存取存储器（DRAM）单元中连接沟槽电容器的方法。 首先，在硅衬底中使用在衬垫氧化物层上包括衬垫氮化物层的掩模层形成沟槽。 沟槽电容器形成在沟槽中。 在电容器的每个沟槽中形成掩埋带。 氮化物衬垫层从沟槽开口被拉回，暴露衬垫氧化物层和可能已经替换衬垫氧化物层的任何带材料围绕沟槽。 带和沟槽侧壁被掺杂以形成电阻连接。 在随后的涉及氧化步骤的浅沟槽隔离（STI）工艺中，硅表面层表面上的暴露的带材料形成不受衬垫氮化物束缚的氧化物，而不会压迫硅衬底。

    EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD
    10.
    发明申请
    EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD 有权
    嵌入式动态随机访问存储器件和方法

    公开(公告)号：US20110180862A1

    公开(公告)日：2011-07-28

    申请号：US12692760

    申请日：2010-01-25

    申请人： Brent A. Anderson ,  John E. Barth, JR. ,  Herbert L. Ho ,  Edward J. Nowak ,  Wayne Trickle

    发明人： Brent A. Anderson ,  John E. Barth, JR. ,  Herbert L. Ho ,  Edward J. Nowak ,  Wayne Trickle

    IPC分类号： H01L27/12 ,  H01L27/108 ,  H01L21/8242

    CPC分类号： H01L21/84 ,  H01L27/1087 ,  H01L27/10894 ,  H01L29/66181

    摘要： Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer. One embodiment of the invention provides an integrated circuit for an embedded dynamic random access memory (eDRAM) comprising: a semiconductor-on-insulator (SOI) wafer including: an n-type substrate; an insulator layer atop the n-type substrate; and an active semiconductor layer atop the insulator layer; a plurality of deep trenches, each extending from a surface of the active semiconductor layer into the n-type substrate; a dielectric liner along a surface of each of the plurality of deep trenches; and an n-type conductor within each of the plurality of deep trenches, the dielectric liner separating the n-type conductor from the n-type substrate; wherein the n-type substrate, the dielectric liner, and the n-type conductor form a buried plate, a node dielectric, and a node plate, respectively, of a cell capacitor.

    摘要翻译： 本发明的实施例提供了一种用于嵌入式动态随机存取存储器（eDRAM），其中可形成这种集成电路的绝缘体上半导体（SOI）晶片的集成电路，以及在这种SOI中形成eDRAM的方法 晶圆。 本发明的一个实施例提供了一种用于嵌入式动态随机存取存储器（eDRAM）的集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：n型衬底; 位于n型衬底顶部的绝缘体层; 和位于绝缘体层顶部的有源半导体层; 多个深沟槽，各自从有源半导体层的表面延伸到n型衬底中; 沿着所述多个深沟槽中的每一个的表面的电介质衬垫; 以及在所述多个深沟槽的每一个内的n型导体，所述电介质衬垫将所述n型导体与所述n型衬底分离; 其中所述n型衬底，所述电介质衬垫和所述n型导体分别形成电池电容器的掩埋板，节点电介质和节点板。