公开(公告)号：US20110051532A1

公开(公告)日：2011-03-03

申请号：US12550848

申请日：2009-08-31

申请人： John E. Barth, JR. ,  Erik A. Nelson

发明人： John E. Barth, JR. ,  Erik A. Nelson

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： G11C7/14 ,  G11C7/065 ,  G11C7/12

摘要： An approach that provides reference level generation with offset compensation for a sense amplifier is described. In one embodiment, an arbitrary reference level is generated to provide an offset that compensates for device mismatch and voltage threshold of a sense amplifier.

摘要翻译： 描述了一种为感测放大器提供具有偏移补偿的参考电平生成的方法。 在一个实施例中，产生任意参考电平以提供补偿读出放大器的器件失配和电压阈值的偏移。

公开(公告)号：US06577548B1

公开(公告)日：2003-06-10

申请号：US10065223

申请日：2002-09-26

申请人： John E. Barth, Jr. ,  Jeffrey H. Dreibelbis ,  Erik A. Nelson

发明人： John E. Barth, Jr. ,  Jeffrey H. Dreibelbis ,  Erik A. Nelson

IPC分类号： G11C702

CPC分类号： G11C11/4099 ,  G11C7/06 ,  G11C7/14 ,  G11C11/4076 ,  G11C11/4091 ,  G11C2207/104

摘要： A method and circuit for a self timed DRAM. The circuit includes interlock circuits coupled to an extension of the DRAM. The extension does not store “real” data but mimics the operations of the DRAM. The interlock circuits, in conjunction with the extension monitor and control read and write timings of the DRAM and self adjust these timings via feedback. To properly track DRAM cell timings, the interlock circuits and extension use the same cell design and load conditions as the DRAM. The method includes: activating a wordline and reference wordline, interlocking the sense amplifiers, column select and write back functions of the primary DRAM array by monitoring the identical reference cells and the state of the bitline in the extension DRAM array.

摘要翻译： 一种自定时DRAM的方法和电路。 该电路包括耦合到DRAM延伸部的互锁电路。 扩展不存储“真实”数据，但模拟DRAM的操作。 互锁电路结合扩展监视器和控制DRAM的读写定时，并通过反馈自行调整这些定时。 为了正确跟踪DRAM单元定时，互锁电路和扩展使用与DRAM相同的单元设计和负载条件。 该方法包括：通过监视相同的参考单元和扩展DRAM阵列中的位线的状态来激活字线和参考字线，使读出放大器互锁，主DRAM阵列的列选择和回写功能。

公开(公告)号：US08125840B2

公开(公告)日：2012-02-28

申请号：US12550848

申请日：2009-08-31

申请人： John E. Barth, Jr. ,  Erik A. Nelson

发明人： John E. Barth, Jr. ,  Erik A. Nelson

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： G11C7/14 ,  G11C7/065 ,  G11C7/12

摘要： An approach that provides reference level generation with offset compensation for a sense amplifier is described. In one embodiment, an arbitrary reference level is generated to provide an offset that compensates for device mismatch and voltage threshold of a sense amplifier.

摘要翻译： 描述了一种为感测放大器提供具有偏移补偿的参考电平生成的方法。 在一个实施例中，产生任意参考电平以提供补偿读出放大器的器件失配和电压阈值的偏移。

公开(公告)号：US20130069678A1

公开(公告)日：2013-03-21

申请号：US13236696

申请日：2011-09-20

申请人： David Grosch ,  Marc D. Knox ,  Erik A. Nelson ,  Brian C. Noble

发明人： David Grosch ,  Marc D. Knox ,  Erik A. Nelson ,  Brian C. Noble

IPC分类号： G01R31/30

CPC分类号： G01R31/30 ,  G01R31/3004

摘要： Method and apparatus for margin testing integrated circuits. The method includes selecting a clock frequency, an operating temperature range and a power supply voltage level for margin testing an integrated circuit wherein one or more of the clock frequency, the operating temperature range and the power supply voltage level is outside of the normal operating conditions of the integrated circuit; applying an asynchronously time varying power supply voltage set to the selected power supply voltage level to the integrated circuit; running the integrated circuit chip at the selected clock frequency and maintaining the integrated circuit within the selected temperature range; applying a continuous test pattern to the integrated circuit; and monitoring the integrated circuit for fails.

摘要翻译： 集成电路边缘检验方法和装置。 该方法包括选择时钟频率，工作温度范围和用于对集成电路进行裕度测试的电源电压电平，其中时钟频率，工作温度范围和电源电压电平中的一个或多个在正常操作条件之外 的集成电路; 对集成电路施加与所选择的电源电压电平设定的异步时变电源电压; 以选定的时钟频率运行集成电路芯片，并将集成电路保持在所选择的温度范围内; 对集成电路施加连续测试图案; 并监控集成电路是否发生故障。

公开(公告)号：US06856569B2

公开(公告)日：2005-02-15

申请号：US10248337

申请日：2003-01-10

申请人： Erik A. Nelson ,  Michael R. Ouellette

发明人： Erik A. Nelson ,  Michael R. Ouellette

IPC分类号： G11C5/00 ,  G11C7/00 ,  G11C29/00

CPC分类号： G11C29/72 ,  G11C29/4401 ,  G11C29/802

摘要： Multiple fuse decompression serial bitstreams support an auxiliary fuseblow capability utilizing on-chip storage and providing a composite capability of embedded memory address/data failure information. A multiple repair capability has an improved compression algorithm to compress fuse data with system level soft-set redundancy, and lends itself to self-repair design, and to provide repairs for temperature sensitive fails. An instruction based tester interface in a fuse control provides shift loaded instructions in which the sequence of test and fuse repair operations is variable to provide flexibility in the manufacturing, test and repair operations.

摘要翻译： 多个熔丝解压缩串行比特流支持利用片上存储的辅助保险丝能力，并提供嵌入式存储器地址/数据故障信息的复合能力。 多重修复功能具有改进的压缩算法，可以用系统级软冗余来压缩熔丝数据，并适用于自修复设计，并提供对温度敏感故障的修复。 保险丝控制中的基于指令的测试器接口提供换档加载指令，其中测试和保险丝修复操作的顺序是可变的，以在制造，测试和修理操作中提供灵活性。

公开(公告)号：US07073100B2

公开(公告)日：2006-07-04

申请号：US10065694

申请日：2002-11-11

申请人： Laura S. Chadwick ,  William R. Corbin ,  Jeffrey H. Dreibelbis ,  Erik A. Nelson ,  Thomas E. Obremski ,  Toshiharu Saitoh ,  Donald L. Wheater

发明人： Laura S. Chadwick ,  William R. Corbin ,  Jeffrey H. Dreibelbis ,  Erik A. Nelson ,  Thomas E. Obremski ,  Toshiharu Saitoh ,  Donald L. Wheater

IPC分类号： G11C29/00

CPC分类号： G11C29/12015 ,  G11C11/401 ,  G11C29/26 ,  G11C2207/104

摘要： A method and system for testing an embedded DRAM that includes DRAM blocks. The method including: generating a test data pattern in a processor based BIST system, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; where for each DRAM block, the write of the test data pattern into the DRAM block is performed before the pause, and the read of the resulting data pattern from each DRAM block is performed after the pause; where at least a portion of the pause of two or more of the DRAM blocks overlap in time; and for each DRAM block comparing the test data pattern to the resulting data pattern.

摘要翻译： 一种用于测试包括DRAM块的嵌入式DRAM的方法和系统。 该方法包括：在基于处理器的BIST系统中为每个DRAM块生成测试数据模式，执行将测试数据模式写入DRAM块，执行预定时间段的暂停，以及执行读取 来自DRAM块的结果数据模式; 对于每个DRAM块，在暂停之前执行将测试数据模式写入DRAM块，并且在暂停之后执行来自每个DRAM块的结果数据模式的读取; 其中两个或更多个DRAM块的暂停的至少一部分在时间上重叠; 并且对于每个DRAM块，将测试数据模式与所得到的数据模式进行比较。

公开(公告)号：US06449200B1

公开(公告)日：2002-09-10

申请号：US09907325

申请日：2001-07-17

申请人： Erik A. Nelson ,  Harold Pilo

发明人： Erik A. Nelson ,  Harold Pilo

IPC分类号： G11C700

CPC分类号： G11C29/28 ,  G11C29/34

摘要： A method and structure for the invention includes an integrated memory structure having a built-in test portion. The integrated memory structure has memory cells, bitlines and wordlines connected to the memory cells, wordline decoders connected to a plurality of the wordlines, bitline restore devices connected to the bitlines for charging the bitlines during read and write operations, and a clock circuit connected to the wordlines. During a test mode the wordline decoders simultaneously select multiple wordlines that the bitline restore devices maintain in an active state and the clock circuit maintains th multiple wordlines and the bitline restore devices in an active state for a period in excess of a normal read cycle. The invention also includes transistors which are connected to the memory cells. The transistors include bitline contacts which are stressed during the test mode.

摘要翻译： 本发明的方法和结构包括具有内置测试部分的集成存储器结构。 集成存储器结构具有连接到存储器单元的存储单元，位线和字线，连接到多个字线的字线解码器，连接到位线的位线恢复器件，用于在读和写操作期间对位线充电;以及时钟电路， 字线。 在测试模式期间，字线解码器同时选择位线恢复装置维持在活动状态的多个字线，并且时钟电路将多个字线和位线恢复装置维持在超过正常读周期的周期内处于活动状态。 本发明还包括连接到存储单元的晶体管。 晶体管包括在测试模式期间受应力的位线触点。

公开(公告)号：US06708298B2

公开(公告)日：2004-03-16

申请号：US09768122

申请日：2001-01-23

申请人： William E. Corbin, Jr. ,  David P. Monty ,  Erik A. Nelson ,  Alan D. Norris ,  Steven W. Tomashot ,  David E. Chapman ,  Timothy E. Fiscus

发明人： William E. Corbin, Jr. ,  David P. Monty ,  Erik A. Nelson ,  Alan D. Norris ,  Steven W. Tomashot ,  David E. Chapman ,  Timothy E. Fiscus

IPC分类号： G11C2900

CPC分类号： G11C29/50012 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C29/50

摘要： A method for testing the data strobe window (DQS) and data valid window (tDV) of a memory device (e.g., a DDR-type memory device) using the window strobe of a testing system.

摘要翻译： 一种使用测试系统的窗口选通来测试存储器件（例如，DDR型存储器件）的数据选通窗口（DQS）和数据有效窗口（tDV）的方法。

公开(公告)号：US08854073B2

公开(公告)日：2014-10-07

申请号：US13236696

申请日：2011-09-20

申请人： David A. Grosch ,  Marc D. Knox ,  Erik A. Nelson ,  Brian C. Noble

发明人： David A. Grosch ,  Marc D. Knox ,  Erik A. Nelson ,  Brian C. Noble

IPC分类号： G01R31/02 ,  G01R31/3187 ,  G01R31/30

CPC分类号： G01R31/30 ,  G01R31/3004

摘要： Method and apparatus for margin testing integrated circuits. The method includes selecting a clock frequency, an operating temperature range and a power supply voltage level for margin testing an integrated circuit wherein one or more of the clock frequency, the operating temperature range and the power supply voltage level is outside of the normal operating conditions of the integrated circuit; applying an asynchronously time varying power supply voltage set to the selected power supply voltage level to the integrated circuit; running the integrated circuit chip at the selected clock frequency and maintaining the integrated circuit within the selected temperature range; applying a continuous test pattern to the integrated circuit; and monitoring the integrated circuit for fails.

摘要翻译： 集成电路边缘检验方法和装置。 该方法包括：选择时钟频率，工作温度范围和用于对集成电路进行裕度测试的电源电压电平，其中时钟频率，工作温度范围和电源电压电平中的一个或多个在正常操作条件之外 的集成电路; 对集成电路施加与所选择的电源电压电平设定的异步时变电源电压; 以选定的时钟频率运行集成电路芯片，并将集成电路保持在所选择的温度范围内; 对集成电路施加连续测试图案; 并监控集成电路是否发生故障。

公开(公告)号：US07237165B2

公开(公告)日：2007-06-26

申请号：US10994496

申请日：2004-11-22

申请人： Laura S. Chadwick ,  William R. Corbin ,  Jeffrey H. Dreibelbis ,  Erik A. Nelson ,  Thomas E. Obremski ,  Toshiharu Saitoh ,  Donald L. Wheater

发明人： Laura S. Chadwick ,  William R. Corbin ,  Jeffrey H. Dreibelbis ,  Erik A. Nelson ,  Thomas E. Obremski ,  Toshiharu Saitoh ,  Donald L. Wheater

IPC分类号： G01R31/28 ,  G11C29/00

CPC分类号： G11C29/12015 ,  G11C11/401 ,  G11C29/26 ,  G11C2207/104

摘要： A system for testing a DRAM includes DRAM blocks, the system further includes a processor based built-in self test system for generating a test data pattern, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block. For each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time, and at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.

摘要翻译： 用于测试DRAM的系统包括DRAM块，该系统还包括用于为每个DRAM块生成测试数据模式的基于处理器的内置自测试系统，将测试数据模式写入DRAM块，执行 暂停预定时间段，并且从DRAM块执行所得数据模式的读取。 对于每个DRAM块，在执行暂停预定时间段之前执行将测试图案写入DRAM块的执行，并且在执行结果之后执行从DRAM块读取得到的数据模式 在预定时间段中的暂停，以及两个或更多个DRAM块的预定时间段的暂停的至少一部分在时间上重叠。