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公开(公告)号：US5995988A
公开(公告)日：1999-11-30
申请号：US131536
申请日：1998-08-10
IPC分类号： H03K19/173 , H03K19/177 , G06F1/04 , G06F7/38
CPC分类号： H03K19/17776 , H03K19/1736 , H03K19/17748
摘要： An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion. Under this mechanism, Y bits are loaded in parallel into the configuration register for increased transfer rate. The architecture of the novel configuration register is such that it is configurable in a serial mode to receive a single serial bit stream of the N bit data frame for downward compatibility.
摘要翻译： 一种用于将配置信息加载到可编程集成电路（例如，FPGA）中的装置，可配置为在同一架构内执行并行加载或位串行加载。 配置信息在每个N个串行位的数据帧中呈现给FPGA。 每个数据帧被分成具有每个Y位的离散串行部分（例如，数据帧包括N / Y部分）。 在并行模式下，这些部分被加载到分段配置寄存器中，每个编程周期一个部分，使得Y位并行加载到分段配置寄存器中。 在并行加载期间的每个编程时钟周期，数据帧部分的所有位同时加载到配置寄存器的段（每个段的第一位位置），使得每个段在每个编程周期接收一位。 然后将配置寄存器的位向下移一个，并为下一个数据帧部分重复循环。 在这种机制下，Y位被并行加载到配置寄存器中，以提高传输速率。 新型配置寄存器的架构使得其可以以串行模式配置以接收N位数据帧的单个串行比特流，用于向下兼容。
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公开(公告)号：US5961576A
公开(公告)日：1999-10-05
申请号：US176626
申请日：1998-10-22
IPC分类号： H03K19/173 , H03K19/177 , G06F1/04 , G06F7/38
CPC分类号： H03K19/17776 , H03K19/1736
摘要： An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion. Under this mechanism, Y bits are loaded in parallel into the configuration register for increased transfer rate. The architecture of the novel configuration register is such that it is configurable in a serial mode to receive a single serial bit stream of the N bit data frame for downward compatibility.
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公开(公告)号：US5844829A
公开(公告)日：1998-12-01
申请号：US985392
申请日：1997-12-04
IPC分类号： H03K19/173 , H03K19/177 , G06F1/04 , G06F7/38
CPC分类号： H03K19/17776 , H03K19/1736 , H03K19/17748
摘要： An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion. Under this mechanism, Y bits are loaded in parallel into the configuration register for increased transfer rate. The architecture of the novel configuration register is such that it is configurable in a serial mode to receive a single serial bit stream of the N bit data frame for downward compatibility.
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公开(公告)号：US5742531A
公开(公告)日：1998-04-21
申请号：US642758
申请日：1996-05-03
IPC分类号： H03K19/173 , H03K19/177 , G06F1/04 , G06F7/38
CPC分类号： H03K19/17776 , H03K19/1736 , H03K19/17748
摘要： An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion. Under this mechanism, Y bits are loaded in parallel into the configuration register for increased transfer rate. The architecture of the novel configuration register is such that it is configurable in a serial mode to receive a single serial bit stream of the N bit data frame for downward compatibility.
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公开(公告)号：US5694056A
公开(公告)日：1997-12-02
申请号：US627815
申请日：1996-04-01
IPC分类号： H03K19/177
CPC分类号： H03K19/17704
摘要： A pipeline frame full detection circuit. The present invention is operable within a system that loads configuration data into an integrated circuit (IC) using a serial data stream and transfer mechanism. Configuration data is transferred into the IC in sequential frames of a specified size for a given IC. The first bit of the configuration data contains a frame full indicator. The configuration data is transferred into a shift register circuit and the last bit position(s) of the shift register circuit, in addition to being stored in the shift register circuit, are shifted along a special frame full pipeline to a control unit. The control unit, upon detecting the frame full indicator, asserts a parallel write command that causes the data of the shift register circuit to be parallel transferred to a receiving column of memory. New configuration data can then be serially shifted into the same shift register circuit after a reset signal. By shifting the frame full indicator through a pipeline, the propagation delay required for the frame full indicator to reach the control unit is significantly reduced. It is this propagation delay that limits the transfer rate of the configuration data into the IC. Therefore, the present invention advantageously reduces this limiting factor.
摘要翻译： 一条流水线全检测电路。 本发明可以在使用串行数据流和传送机制将配置数据加载到集成电路（IC）的系统中操作。 对于给定的IC，配置数据以指定大小的连续帧传送到IC。 配置数据的第一位包含一个帧完整指示符。 配置数据被传送到移位寄存器电路中，并且除了存储在移位寄存器电路之外，移位寄存器电路的最后位位置沿特殊帧完整流水线移动到控制单元。 控制单元在检测到帧全指示符时，断言并行写入命令，使得移位寄存器电路的数据被并行地传送到存储器的接收列。 复位信号后，新的配置数据可以被串行移位到相同的移位寄存器电路中。 通过将帧满指示符移动通过流水线，帧全指示器到达控制单元所需的传播延迟显着降低。 正是这种传播延迟将配置数据的传输速率限制在IC中。 因此，本发明有利地减少了这个限制因素。
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公开(公告)号：US5712579A
公开(公告)日：1998-01-27
申请号：US543693
申请日：1995-10-16
IPC分类号： H03K5/15 , H03K19/177 , H03K19/00
CPC分类号： H03K19/1774 , H03K19/17704 , H03K5/1502
摘要： A clock distribution network and mechanisms therein for an integrated circuit (IC) including an edge clock and distribution system for same. The invention includes a deskewed clock distribution network for circuits situated in columns wherein buffering is done in columns less than half of the IC length. The mechanism allows each of at least eight vertical column distribution lines to couple with any horizontal clock supply line of at least eight lines. The horizontal clock supply lines include local interconnect inputs. To increase clock source signals, special lines, Kx lines, are provided that are buffered and traverse directionally in 1/4 IC lengths from the top down, bottom up, and midsection both up and down. Kx lines can be sourced from carry signals, IOBs, interconnects, or from an edge clock and supply to clock lines, longlines, or interconnect lines. Kx lines allow vertical signal displacement, e.g., for clock signals, etc., within the chip. An edge clock is provided that is not deskewed and is directly coupled to an edge clock distribution system along the left and right edges of the IC to supply a clock signal to an entire edge or half of an edge with less delay relative to the deskewed clock. Also, a super fast edge clock is provided for very high speed circuits.
摘要翻译： 一种用于集成电路（IC）的时钟分配网络及其机构，包括用于其的边缘时钟和分配系统。 本发明包括用于位于列中的电路的偏斜校正时钟分配网络，其中缓冲在小于IC长度的一半的列中进行。 该机构允许至少八个垂直列分配线中的每一个与至少八行的任何水平时钟供应线耦合。 水平时钟电源线包括局部互连输入。 为了增加时钟源信号，提供专门的线路Kx线，它们在+ E中进行缓冲和定向移动，从上到下，从上到下和上下中间的1/4 + EE IC长度。 Kx线可以来自进位信号，IOB，互连或从边沿时钟提供到时钟线，延长线或互连线。 Kx线允许垂直信号位移，例如芯片内的时钟信号等。 提供边缘时钟，其不进行去校正，并且沿着IC的左边缘和右边缘直接耦合到边缘时钟分配系统，以将时钟信号提供给相对于偏移校正时钟的延迟较小的边缘的整个边缘或一半 。 此外，为超高速电路提供超快速时钟。
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7.发明授权公开(公告)号：US08966253B1
公开(公告)日：2015-02-24
申请号：US12791668
申请日：2010-06-01
CPC分类号： H04L63/123 , G06F9/30145 , G06F21/572 , G06F21/76
摘要： A method and apparatus for authenticating a bitstream used to configure programmable devices are described. In an example, the bitstream is received via a configuration port of the programmable device, the bitstream including instructions for programming configuration registers of the programmable device and at least one embedded message authentication code (MAC). At least a portion of the instructions is initially stored in a memory of the programmable device without programming the configuration registers. At least one actual MAC is computed based on the bitstream using a hash algorithm. The at least one actual MAC is compared with the at least one embedded MAC, respectively. Each instruction stored in the memory is executed to program the configuration registers until any one of the at least one actual MAC is not the same as a corresponding one of the at least one embedded MAC, after which any remaining instructions in the memory are not executed.
摘要翻译： 描述用于认证用于配置可编程设备的比特流的方法和装置。 在一个示例中，经由可编程设备的配置端口接收比特流，比特流包括用于编程可编程设备的配置寄存器和至少一个嵌入式消息认证码（MAC）的指令。 指令的至少一部分最初被存储在可编程设备的存储器中，而不对配置寄存器进行编程。 使用散列算法基于比特流计算至少一个实际的MAC。 将至少一个实际的MAC分别与至少一个嵌入式MAC进行比较。 执行存储在存储器中的每个指令以对配置寄存器进行编程，直到至少一个实际MAC中的任何一个与至少一个嵌入式MAC中的对应的一个不相同，之后不执行存储器中的任何剩余指令 。
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8.发明授权Programmable integrated circuit and a method of enabling the detection of tampering with data provided to a programmable integrated circuit 有权可编程集成电路和一种能够检测篡改提供给可编程集成电路的数据的方法公开(公告)号：US08909941B1
公开(公告)日：2014-12-09
申请号：US13077814
申请日：2011-03-31
IPC分类号： G06F21/00
CPC分类号： H04L63/1466 , G06F21/64 , G06F21/76
摘要： A method of enabling detection of tampering with data provided to a programmable integrated circuit is described. The method comprises modifying a portion of the data to establish randomness in the data; and inserting, by a computer, a redundancy check value in the portion, wherein the redundancy check value is based upon the modified portion of the data. A programmable integrated circuit is also described.
摘要翻译： 描述了能够检测到提供给可编程集成电路的数据的篡改的方法。 该方法包括修改数据的一部分以在数据中建立随机性; 并且由计算机插入所述部分中的冗余校验值，其中所述冗余校验值基于所述数据的修改部分。 还描述了可编程集成电路。
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公开(公告)号：US08416950B1
公开(公告)日：2013-04-09
申请号：US13082271
申请日：2011-04-07
IPC分类号： H04L29/06
CPC分类号： H04L9/0866
摘要： An integrated circuit includes a fingerprint element and a decryption circuit. The fingerprint element generates a fingerprint, where the fingerprint is reproducible and represents an inherent manufacturing process characteristic unique to the integrated circuit device. The decryption circuit decrypts, using a decryption key that is based on the fingerprint, an encrypted data in order to extract data. In one embodiment, the propagation delay of various circuit elements are used to generate the fingerprint. In another embodiment, the specific frequency of an oscillator is used to generate the fingerprint. In yet another embodiment, a ratio of measurable values is used to generate the fingerprint. In another embodiment, differences in transistor threshold voltages are used to generate the fingerprint. In yet another embodiment, variations in line widths are used to generate the fingerprint.
摘要翻译： 集成电路包括指纹元件和解密电路。 指纹元件产生指纹，其中指纹是可重现的，并且表示集成电路设备独有的固有制造工艺特性。 解密电路使用基于指纹的解密密钥解密加密数据，以提取数据。 在一个实施例中，各种电路元件的传播延迟被用于产生指纹。 在另一个实施例中，使用振荡器的特定频率来生成指纹。 在另一个实施例中，使用可测量值的比例来生成指纹。 在另一个实施例中，晶体管阈值电压的差异用于产生指纹。 在另一个实施例中，使用线宽的变化来生成指纹。
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公开(公告)号：US08104012B1
公开(公告)日：2012-01-24
申请号：US12363721
申请日：2009-01-31
申请人： Matthew H. Klein , Edward S. McGettigan , Stephen M. Trimberger , James M. Simkins , Brian D. Philofsky , Subodh Gupta
发明人： Matthew H. Klein , Edward S. McGettigan , Stephen M. Trimberger , James M. Simkins , Brian D. Philofsky , Subodh Gupta
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054 , G06F2217/62
摘要： Dynamic power savings and efficient use of resources are achieved in a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) by receiving a design netlist specifying a circuit including clock signals, clock buffers, clock enable signals and synchronous elements, examining the design netlist to identify synchronous elements coupled to common clock and clock enable signals, cutting the clock signals to the synchronous elements to form a modified design netlist, inserting gated clock buffers into the modified netlist to output gated clock signals to the synchronous elements, responsive to the clock enable signals, and performing placement and routing on the modified netlist. A system for performing the method on an EDA tool is provided. The methods may be provided as executable instructions stored on a computer readable medium which cause a programmable processor to perform the methods.
摘要翻译： 在诸如现场可编程门阵列（FPGA）或复杂可编程逻辑器件（CPLD）的可编程逻辑器件（PLD）中实现动态功率节省和资源的有效利用，通过接收指定包括时钟信号，时钟缓冲器的电路的设计网表 ，时钟使能信号和同步元件，检查设计网表以识别耦合到公共时钟和时钟使能信号的同步元件，将时钟信号切割到同步元件以形成修改后的设计网表，将门控时钟缓冲器插入修改的网表以输出 门控时钟信号到同步元件，响应于时钟使能信号，并在修改的网表上执行放置和布线。 提供了一种用于在EDA工具上执行该方法的系统。 可以将这些方法提供为存储在计算机可读介质上的可执行指令，其使可编程处理器执行该方法。
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