公开(公告)号：US20130218316A1

公开(公告)日：2013-08-22

申请号：US13401295

申请日：2012-02-21

申请人： John H. ZHANG ,  Cindy GOLDBERG

发明人： John H. ZHANG ,  Cindy GOLDBERG

IPC分类号： G06F19/00 ,  H01L21/306

CPC分类号： B24B37/013 ,  B24B49/12 ,  H01L22/12 ,  H01L22/26

摘要： A semiconductor processing apparatus includes a semiconductor processing station for a semiconductor wafer, and an endpoint detector associated with the semiconductor processing station. The endpoint detector includes a non-contact probe configured to probe the semiconductor wafer, an optical transmitter configured to transmit an optical signal to the non-contact probe, and an optical receiver configured to receive a reflected optical signal from the non-contact probe. The controller controls the semiconductor processing station based on the reflected optical signal.

摘要翻译： 半导体处理装置包括半导体晶片的半导体处理站和与半导体处理站相关联的端点检测器。 端点检测器包括配置成探测半导体晶片的非接触探针，被配置为将光信号传输到非接触探针的光发射器，以及被配置为从非接触探针接收反射光信号的光接收器。 控制器基于反射光信号控制半导体处理站。

公开(公告)号：US20120313144A1

公开(公告)日：2012-12-13

申请号：US13494965

申请日：2012-06-12

申请人： John H. ZHANG ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

发明人： John H. ZHANG ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/7781

摘要： A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.

摘要翻译： 一种半导体器件，其具有位于源极区域和漏极区域之间的与栅极电极的两侧相邻的凹部中的栅极。 沟道区域低于源极区域的大部分以及漏极区域和整个栅极电极的大部分。

公开(公告)号：US20120313153A1

公开(公告)日：2012-12-13

申请号：US13494973

申请日：2012-06-12

申请人： John H. ZHANG ,  Lawrence A. CLEVENGER ,  Carl J. RADENS ,  Yiheng XU

发明人： John H. ZHANG ,  Lawrence A. CLEVENGER ,  Carl J. RADENS ,  Yiheng XU

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/7834 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/31116 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/665 ,  H01L29/6659

摘要： According to one embodiment of the invention, the gate contact is formed by a selective deposition on the gate electrode. One acceptable technique for the selective deposition is by plating. Plating is one process by which a metal structure, such as a gate contact, may be formed directly on the gate electrode. The plating is carried out by immersing the semiconductor die in a plating solution with the gate electrode exposed. The gate contact is plated onto the gate electrode and thus is ensured of being fully aligned exactly to the gate electrode. After this, the appropriate dielectric layers are formed adjacent the gate contact and over the source and drain to ensure that the gate electrode is electrically isolated from other components of the transistor.

摘要翻译： 根据本发明的一个实施例，通过在栅电极上的选择性沉积形成栅极接触。 用于选择性沉积的一种可接受的技术是通过电镀。 电镀是可以直接在栅电极上形成诸如栅极接触的金属结构的一个过程。 通过将半导体管芯浸渍在露出电极的电镀液中来进行电镀。 栅极接触电镀在栅电极上，因此确保与栅电极完全对准。 之后，在栅极接触点和源极和漏极之间形成适当的电介质层，以确保栅电极与晶体管的其它部件电隔离。