公开(公告)号：US20080232159A1

公开(公告)日：2008-09-25

申请号：US12109081

申请日：2008-04-24

申请人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

发明人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/18 ,  H01L27/101 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145

摘要： The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.

公开(公告)号：US07715248B2

公开(公告)日：2010-05-11

申请号：US12109081

申请日：2008-04-24

申请人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

发明人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

IPC分类号： G11C7/00 ,  G11C7/22

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/18 ,  H01L27/101 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145

摘要： The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.

摘要翻译： 本发明涉及诸如ROM或EPROM的非易失性存储器，其中存储器的信息密度相对于包括两个逻辑状态器件的常规非易失性存储器而增加。 具体地，本发明的非易失性存储器包括嵌入在热导率为约1W / m-K以下的材料中的SiN / TaN / SiN薄膜电阻器; 以及耦合到电阻器的非线性含Si器件。 读写电路和操作也在本申请中提供。

公开(公告)号：US20080197337A1

公开(公告)日：2008-08-21

申请号：US12109085

申请日：2008-04-24

申请人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

发明人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

IPC分类号： H01L47/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/18 ,  H01L27/101 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145

摘要： The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.

摘要翻译： 本发明涉及诸如ROM或EPROM的非易失性存储器，其中存储器的信息密度相对于包括两个逻辑状态器件的常规非易失性存储器而增加。 具体地，本发明的非易失性存储器包括嵌入在热导率为约1W / m-K以下的材料中的SiN / TaN / SiN薄膜电阻器; 以及耦合到电阻器的非线性含Si器件。 读写电路和操作也在本申请中提供。

公开(公告)号：US07381981B2

公开(公告)日：2008-06-03

申请号：US11161332

申请日：2005-07-29

申请人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

发明人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

IPC分类号： H01L29/02 ,  H01L47/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/18 ,  H01L27/101 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145

摘要： The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.

摘要翻译： 本发明涉及诸如ROM或EPROM的非易失性存储器，其中存储器的信息密度相对于包括两个逻辑状态器件的常规非易失性存储器而增加。 具体地，本发明的非易失性存储器包括嵌入在热导率为约1W / m-K以下的材料中的SiN / TaN / SiN薄膜电阻器; 以及耦合到电阻器的非线性含Si器件。 读写电路和操作也在本申请中提供。

公开(公告)号：US07880158B2

公开(公告)日：2011-02-01

申请号：US12109085

申请日：2008-04-24

申请人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

发明人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

IPC分类号： H01L47/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/18 ,  H01L27/101 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145

摘要： The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.

摘要翻译： 本发明涉及诸如ROM或EPROM的非易失性存储器，其中存储器的信息密度相对于包括两个逻辑状态器件的常规非易失性存储器而增加。 具体地，本发明的非易失性存储器包括嵌入在热导率为约1W / m-K以下的材料中的SiN / TaN / SiN薄膜电阻器; 以及耦合到电阻器的非线性含Si器件。 读写电路和操作也在本申请中提供。

公开(公告)号：US08237463B1

公开(公告)日：2012-08-07

申请号：US13034758

申请日：2011-02-25

申请人： Fen Chen ,  Kai D. Feng ,  Zhong-Xiang He

发明人： Fen Chen ,  Kai D. Feng ,  Zhong-Xiang He

IPC分类号： H03K19/003

CPC分类号： H03K19/00307

摘要： Managing reliability of a circuit that includes a plurality of duplicate components, with less than all of the components being active at any time during circuit operation, where reliability is managed by operating, by the circuit, with a first set of components that includes a predefined number of components; selecting, without altering circuit performance and in accordance with a circuit reliability protocol, a second set of components with which to operate, including activating an inactive component and deactivating an active component of the first set of components; and operating, by the circuit, with the second set of components.

摘要翻译： 管理包括多个重复部件的电路的可靠性，其中小于所有组件在电路操作期间的任何时间处于活动状态，其中可靠性由电路通过第一组组件来管理，该组件包括预定义的 组件数量; 根据电路可靠性协议选择不改变电路性能的第二组组件，包括激活非活动组件和去激活第一组组件的活动组件; 并通过电路与第二组元件一起操作。

公开(公告)号：US20090107220A1

公开(公告)日：2009-04-30

申请号：US11926241

申请日：2007-10-29

申请人： Fen Chen ,  Kai D. Feng

发明人： Fen Chen ,  Kai D. Feng

IPC分类号： G01N25/56

CPC分类号： G01N27/223

摘要： A design structure for an on-chip real-time moisture detection circuitry for monitoring ingress of moisture into an integrated circuit chip during the operational lifetime of the chip. The moisture detection circuitry includes one or more moisture-sensing units and a common moisture monitor for monitoring the state of each moisture-sensing units. The moisture monitor can be configured to provided a real-time moisture-detected signal for signaling that moisture ingress into the integrated circuit chip has occurred.

摘要翻译： 一种片上实时水分检测电路的设计结构，用于在芯片的使用寿命期间监测水分进入集成电路芯片的情况。 湿度检测电路包括一个或多个湿度感测单元和用于监测每个湿度感测单元的状态的公共湿度监视器。 水分监测器可以被配置为提供实时湿度检测信号，用于发信号通知已经发生湿气进入集成电路芯片。

公开(公告)号：US07345503B2

公开(公告)日：2008-03-18

申请号：US11427798

申请日：2006-06-30

申请人： Fen Chen ,  Kai D. Feng ,  Robert J. Gauthier, Jr. ,  Tom C. Lee

发明人： Fen Chen ,  Kai D. Feng ,  Robert J. Gauthier, Jr. ,  Tom C. Lee

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/018571

摘要： A method for trimming impedance matching devices in high-speed circuits includes determining an electrical parameter associated with a first tantalum nitride (TaN) resistor used as an impedance matching device in the circuit under test, and comparing the determined electrical parameter associated with the first TaN resistor to a desired design value of the electrical parameter. The resistance value of the first TaN resistor is altered by application of a trimming voltage thereto, wherein the trimming voltage is based on a voltage-resistance characteristic curve of the first TaN resistor. It is then determined whether the altered resistance value of the first TaN resistor causes the electrical parameter to equal the desired design value thereof, and the altering of the resistance value of the first TaN resistor by application of a trimming voltage is repeated until the electrical parameter equals the desired design value thereof.

摘要翻译： 一种用于微调高速电路中的阻抗匹配装置的方法包括：确定与在被测电路中用作阻抗匹配装置的第一氮化钽（TaN）电阻相关联的电参数，并将确定的与第一TaN相关的电参数进行比较 电阻到所需的电参数设计值。 通过施加微调电压来改变第一TaN电阻器的电阻值，其中微调电压基于第一TaN电阻器的耐电压特性曲线。 然后确定第一TaN电阻器的改变的电阻值是否使电参数等于其期望的设计值，并且重复通过施加微调电压来改变第一TaN电阻器的电阻值，直到电参数 等于其期望的设计值。

公开(公告)号：US20130049793A1

公开(公告)日：2013-02-28

申请号：US13222306

申请日：2011-08-31

申请人： Fen Chen ,  Roger A. Dufresne ,  Kai D. Feng ,  Richard J. St-Pierre

发明人： Fen Chen ,  Roger A. Dufresne ,  Kai D. Feng ,  Richard J. St-Pierre

IPC分类号： G01R31/26 ,  G01R31/02

CPC分类号： G01R31/2858

摘要： A testing structure, system and method for monitoring electro-migration (EM) performance. A system is described that includes an array of testing structures, wherein each testing structure includes: an EM resistor having four point resistive measurement, wherein a first and second terminals provide current input and a third and fourth terminals provide a voltage measurement; a first transistor coupled to a first terminal of the EM resistor for supplying a test current; the voltage measurement obtained from a pair of switching transistors whose gates are controlled by a selection switch and whose drains are utilized to provide a voltage measurement across the third and fourth terminals. Also included is a decoder for selectively activating the selection switch for one of the array of testing structures; and a pair of outputs for outputting the voltage measurement of a selected testing structure.

摘要翻译： 用于监测电迁移（EM）性能的测试结构，系统和方法。 描述了包括测试结构阵列的系统，其中每个测试结构包括：具有四点电阻测量的EM电阻器，其中第一和第二端子提供电流输入，第三和第四端子提供电压测量; 耦合到所述EM电阻器的第一端子以提供测试电流的第一晶体管; 由一对开关晶体管获得的电压测量，其栅极由选择开关控制，并且其漏极用于在第三和第四端子处提供电压测量。 还包括用于选择性地激活测试结构阵列之一的选择开关的解码器; 以及用于输出所选择的测试结构的电压测量的一对输出。

公开(公告)号：US07571637B2

公开(公告)日：2009-08-11

申请号：US11926241

申请日：2007-10-29

申请人： Fen Chen ,  Kai D. Feng

发明人： Fen Chen ,  Kai D. Feng

IPC分类号： G01N5/02

CPC分类号： G01N27/223

摘要： A design structure for an on-chip real-time moisture detection circuitry for monitoring ingress of moisture into an integrated circuit chip during the operational lifetime of the chip. The moisture detection circuitry includes one or more moisture-sensing units and a common moisture monitor for monitoring the state of each moisture-sensing units. The moisture monitor can be configured to provided a real-time moisture-detected signal for signaling that moisture ingress into the integrated circuit chip has occurred.

摘要翻译： 一种片上实时水分检测电路的设计结构，用于在芯片的使用寿命期间监测水分进入集成电路芯片的情况。 湿度检测电路包括一个或多个湿度感测单元和用于监测每个湿度感测单元的状态的公共湿度监视器。 水分监测器可以被配置为提供实时湿度检测信号，用于发信号通知已经发生湿气进入集成电路芯片。