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公开(公告)号：US5486795A
公开(公告)日：1996-01-23
申请号：US051134
申请日：1993-04-22
申请人： John R. Spence , Rajiv Gupta , Mingming Zhang
发明人： John R. Spence , Rajiv Gupta , Mingming Zhang
CPC分类号： H03B5/364
摘要： The LOW POWER CRYSTAL OSCILLATOR shown here reduces power consumption of a Pierce oscillator which has an inverter preferably made of an NFET N0 and a PFET P0 in series. A load, preferably an NFET N1 with its gate wired to its source, is placed in parallel with a switch, preferably a PFET P1, between P0 and Vcc. A clamp, preferably a PFET P2 with its gate wired to its source, is placed in parallel with a switch, preferably an NFET N2, between N0 and ground. The switches are enabled during power-up, thereby providing quick turn-on of the oscillator. They are then disabled, thereby reducing the voltage across the crystal XTAL and consequently reducing the power consumed.
摘要翻译： 这里所示的低功率晶体振荡器降低了具有由NFET N0和PFET P0串联的变换器的皮尔斯振荡器的功耗。 负载，优选地，其栅极连接到其源极的NFET N1与P0和Vcc之间的开关（优选PFET P1）平行放置。 夹具，优选地是其栅极连接到其源极的PFET P2与N0和地之间的开关，优选NFET N2平行放置。 开关在上电时使能，从而提供快速开启振荡器。 然后它们被禁用，从而降低晶体XTAL两端的电压，从而降低功耗。
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公开(公告)号：US5455542A
公开(公告)日：1995-10-03
申请号：US155500
申请日：1993-11-22
申请人： John R. Spence , Rajiv Gupta , Ming M. Zhang
发明人： John R. Spence , Rajiv Gupta , Ming M. Zhang
CPC分类号： H03K3/0307
摘要： An oscillator circuit provides a symmetrical signal without halving the frequency of a crystal oscillator 12. The input 14 of the crystal oscillator 12 is low pass filtered, and the output 18 of the filter 16 is differential voltage compared with the input 14 of the crystal oscillator 12. The output 22 of the differential voltage comparator 20 is symmetrical and of the same frequency as the crystal oscillator 12. The crystal oscillator 12 is preferably a Pierce oscillator.
摘要翻译： 振荡器电路提供对称信号而不使晶体振荡器12的频率减半。晶体振荡器12的输入端14被低通滤波，滤波器16的输出端18与晶体振荡器的输入端14相比是差分电压 差分电压比较器20的输出22是对称的，并且具有与晶体振荡器12相同的频率。晶体振荡器12优选地是皮尔斯振荡器。
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公开(公告)号：US08172265B2
公开(公告)日：2012-05-08
申请号：US12782734
申请日：2010-05-19
申请人： Tom R. James , John R. Spence
发明人： Tom R. James , John R. Spence
IPC分类号： G01C5/00
摘要： A surveillance module may be deployed from a vehicle. The vehicle to deploy the surveillance module includes a first portion configured to accommodate a user to operate the vehicle. A second portion includes a module configured to accommodate the user and comprising a roof and an entrance accessible through an interior of the vehicle from the first portion. The second portion also includes a lifting mechanism coupled to the module and operable to move the module vertically from a retracted position to an extended position. A third portion defines an opening to accommodate the module, wherein the roof of the module couples to a periphery of the opening in the retracted position.
摘要翻译： 可以从车辆部署监视模块。 部署监视模块的车辆包括构造成容纳用户操作车辆的第一部分。 第二部分包括被配置为容纳使用者并且包括屋顶和可从第一部分通过车辆内部接近的入口的模块。 第二部分还包括联接到模块并且可操作以将模块从缩回位置垂直移动到延伸位置的提升机构。 第三部分限定开口以容纳模块，其中模块的顶部在缩回位置处联接到开口的周边。
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公开(公告)号：US4686652A
公开(公告)日：1987-08-11
申请号：US801650
申请日：1985-11-25
申请人： John R. Spence
发明人： John R. Spence
CPC分类号： G11C14/00
摘要： A memory cell circuit for storing the state of a digital signal on a data bus in response to an address signal. The memory cell has a store cycle with a repeating series of recurring store cycle sequences, each store cycle sequence having a (HIV) high-voltage timing signal during a first interval, and first and second store timing signals. The memory cell circuit also has a recall cycle. Each recall cycle has a memory reset signal to pre-set the state of the memory cell circuit during a first interval, a recall output signal at a predetermined voltage level and a recall transfer signal. The memory cell comprises a volatile RAM cell having a flip-flop providing an output signal at an output terminal. The flip-flop also has a RESET TERMINAL responsive to a reset signal for forcing the flip-flop to assume a predetermined state in response to the memory reset signal and a SET TERMINAL responsive to a set signal for setting the state of the volatile RAM cell in a recall sequence. A non-volatile RAM element has a rectifier capacitor means responsive to the high voltage timing signal for precharging to a first state during the first timing interval of each store cycle. Transfer control circuit means is responsive to the first store timing signal to discharge the capacitor in response to the flip-flop output signal being in a first state. The capacitor remains precharged in response to the flip-flop output signal being in a second state. A charge storage memory stores a state corresponding to the charge state of the capacitor into a non-volatile charge storage element. The charge storage memory provides a set signal corresponding to the state of the capacitor. The transfer control circuit couples the set signal to set the state of the flip-flop to correspond to the charged state of the charge storage device.
摘要翻译： 一种用于响应于地址信号而在数据总线上存储数字信号的状态的存储单元电路。 存储器单元具有存储循环，其具有重复的循环存储循环序列，每个存储循环序列在第一间隔期间具有（HIV）高电压定时信号，以及第一和第二存储定时信号。 存储单元电路也具有调用循环。 每个调用循环具有存储器复位信号，以在第一间隔期间预设存储单元电路的状态，预定电压电平的调用输出信号和调用转移信号。 存储单元包括具有在输出端提供输出信号的触发器的易失性RAM单元。 触发器还具有响应于复位信号的RESET TERMIN，用于迫使触发器响应于存储器复位信号而呈现预定状态，并且响应于设置信号的SET TERMINAL来设置易失性RAM单元的状态 在召回序列中。 非易失性RAM元件具有整流电容器装置，其响应于高电压定时信号，以在每个存储周期的第一定时间隔期间预充电到第一状态。 转移控制电路装置响应于第一存储定时信号，以响应于触发器输出信号处于第一状态而放电电容器。 响应于触发器输出信号处于第二状态，电容器保持预充电。 电荷存储存储器将与电容器的充电状态相对应的状态存储到非易失性电荷存储元件中。 电荷存储存储器提供对应于电容器的状态的设定信号。 传送控制电路将设置信号耦合以将触发器的状态设置为对应于电荷存储装置的充电状态。
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公开(公告)号：USD265644S
公开(公告)日：1982-08-03
申请号：US141875
申请日：1980-04-21
申请人： John R. Spence
设计人： John R. Spence
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公开(公告)号：US4048632A
公开(公告)日：1977-09-13
申请号：US664222
申请日：1976-03-05
申请人： John R. Spence
发明人： John R. Spence
摘要： A compact circuit for selectively controlling the operation of a plurality of metal oxide semiconductor field effect transistors (MOSFETs) which drive a readout display, such as that found in a hand-held calculator, or the like. The circuit includes an internal power supply to develop a driving voltage (V.sub.gg), the magnitude of which is substantially boosted with respect to that of the calculator operating voltage (V.sub.DD). The circuit also includes an improved strobe driver connected between the display and the power supply to selectively apply the boosted driving voltage to a control electrode of any one of the plurality of MOSFETs.
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公开(公告)号：US20110101719A1
公开(公告)日：2011-05-05
申请号：US12782734
申请日：2010-05-19
申请人： Tom R. James , John R. Spence
发明人： Tom R. James , John R. Spence
摘要： A surveillance module may be deployed from a vehicle. The vehicle to deploy the surveillance module includes a first portion configured to accommodate a user to operate the vehicle. A second portion includes a module configured to accommodate the user and comprising a roof and an entrance accessible through an interior of the vehicle from the first portion. The second portion also includes a lifting mechanism coupled to the module and operable to move the module vertically from a retracted position to an extended position. A third portion defines an opening to accommodate the module, wherein the roof of the module couples to a periphery of the opening in the retracted position.
摘要翻译： 可以从车辆部署监视模块。 部署监视模块的车辆包括构造成容纳用户操作车辆的第一部分。 第二部分包括被配置为容纳使用者并且包括屋顶和可从第一部分通过车辆内部接近的入口的模块。 第二部分还包括联接到模块并且可操作以将模块从缩回位置垂直移动到延伸位置的提升机构。 第三部分限定开口以容纳模块，其中模块的顶部在缩回位置处联接到开口的周边。
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公开(公告)号：US5613680A
公开(公告)日：1997-03-25
申请号：US488736
申请日：1995-06-08
CPC分类号： G07C15/005 , A63F3/0645 , A63F2009/242
摘要： The present invention is directed to game cards and systems for tracking game cards. A computer tracking system is used which includes game or lottery type cards which must be activated to be eligible for a particular game or event. The activation step includes reading of a unique serial number or other identification code uniquely identifying the card. With this system, surplus game cards can be disposed of when they have not been activated. This simplifies tracking of sales of game cards and simplifies the distribution of funds to various parties in the sale and distribution chain.
摘要翻译： 本发明涉及用于跟踪游戏卡的游戏卡和系统。 使用计算机跟踪系统，其包括必须被激活以具有特定游戏或事件资格的游戏或彩票类型卡。 激活步骤包括读取独特的序列号或唯一识别该卡的其他识别码。 使用这个系统，剩余的游戏卡在没有激活的时候可以被处理掉。 这简化了游戏卡的销售跟踪，简化了销售和分销链中各方的资金分配。
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公开(公告)号：US4504745A
公开(公告)日：1985-03-12
申请号：US388044
申请日：1982-06-14
IPC分类号： H03K19/094 , H03K19/096 , H03K17/693
CPC分类号： H03K19/09429 , H03K19/0963
摘要： A tri-state driver circuit is provided having a first clock node; and a second clock node, the first and second clock nodes being adapted to receive first and second clock signals from respectively first and second clock signal sources, the first clock signal being periodic and having a first and second logic level, the second clock signal being the complement of the first clock signal. A float node is included and is adapted to receive a complement float signal (F) having a first and second logic level from a float signal source, an array of input nodes are also included, each input node being adapted to receive an input signal having a first and second logic level from a respective input signal source. An array of output nodes are included, each output node corresponding to a respective input node and being coupled to a respective load. The clocked tri-state driver circuit comprises: an enable node, a clocked power switch means coupled to the first and second clock signal nodes and the float node; the clocked power switch means being responsive to the first and second clock signal and the complement float signal first logic level for providing a clocked enable signal to the enable node; an array of driver circuit means for conditioning and transferring each respective input signal from a corresponding input node as an output signal to a corresponding output node when enabled, each respective driver circuit means being coupled to the enable node and enabled by the clocked enable signal, each respective driver circuit means being decoupled from the corresponding output node when not enabled, whereby the tri-state driver circuit operates to provide an array of output signals to an array of corresponding output nodes when enabled by the clocked enable signal first logic level at the enable node; the tri-state driver circuit also operating to decouple the output signals from the corresponding output nodes in response to the clocked enable signal second logic level thereby permitting the corresponding output nodes to be conditioned by voltage sources other than the tri-state driver circuit.
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公开(公告)号：US4450368A
公开(公告)日：1984-05-22
申请号：US332634
申请日：1981-12-21
申请人： John R. Spence
发明人： John R. Spence
CPC分类号： H03K5/2481
摘要： An ac coupled, chopper stabilized differential comparator circuit characterized receiving a differential signal voltage applied between a signal input terminal and a reference signal input terminal, providing differential outputs at a first and second differential output terminal and being characterized as operating from a voltage source with respect to a reference potential comprising: amplifier means, characterized by a first stage differential amplifier having, a first channel amplifier having an input terminal and an output terminal. The first channel amplifier output terminal is connected to the first differential output terminal. The first stage differential amplifier also has a second channel amplifier having an input terminal and an output terminal. The second channel amplifier output terminal is connected to the second differential output terminal. The gain of the second channel amplifier is essentially equal to the gain of the first channel amplifier. A first channel input capacitor having a first and second terminal is included, the second terminal being connected to the first channel amplifier input terminal. A second channel input capacitor is also included, having a first and second terminal, the second terminal being connected to the second channel amplifier input terminal. A clock signal means is included, having a first clock signal and a second clock signal, along with means responsive to the first clock signal for connecting the first and second channel amplifier output terminals to their respective input terminals. Signal input selection means is included for connecting the signal input terminal to the first channel input capacitor first terminal, and for connecting the reference signal input terminal to the second channel input capacitor first terminal, in response to only the first clock signal. The signal input selection means connects the signal input terminal to the second channel input capacitor first terminal and also connects the reference signal input terminal to the first channel input capacitor first terminal in response to the second clock signal; whereby the differential signal voltage between the signal input terminal and the reference signal input terminal is amplified. The amplified differential voltage is provided as a differential output voltage between the first and second channel amplifier output terminals having reduced amplifier offset voltage error.
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